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RELEASE_NOTES: update and fix formatting

This commit is contained in:
Sebastien Bourdeauducq 2021-07-05 21:22:34 +08:00
parent 0257ecc332
commit 29fd58e34b
1 changed files with 11 additions and 7 deletions
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18
RELEASE_NOTES.rst
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@ -7,20 +7,24 @@ ARTIQ-7
------- -------
Highlights: Highlights:
* Support for Kasli-SoC, a new EEM carrier based on a Zynq SoC, enabling much faster kernel execution.
* Softcore targets now use the RISC-V architecture (VexRiscv) instead of OR1K (mor1kx).
* WRPLL * WRPLL
* ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912
* Phaser:
- Improved documentation
- Expose the DAC coarse mixer and sif_sync
- Exposes upconverter calibration and enabling/disabling of upconverter LO & RF outputs.
* Compiler: * Compiler:
- Supports kernel decorator with paths. - Supports kernel decorator with paths.
- Faster compilation for large arrays/lists. - Faster compilation for large arrays/lists.
* Phaser:
- Improved documentation
- Expose the DAC coarse mixer and ``sif_sync``
- Exposes upconverter calibration and enabling/disabling of upconverter LO & RF outputs.
* ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912
Breaking changes: Breaking changes:
* Updated Phaser-Upconverter default frequency 2.875 GHz. The new default uses the target PFD * Updated Phaser-Upconverter default frequency 2.875 GHz. The new default uses the target PFD
frequency of the hardware design. frequency of the hardware design.
* `Phaser.init()` now disables all Kasli-oscillators. This avoids full power RF output being * ``Phaser.init()`` now disables all Kasli-oscillators. This avoids full power RF output being
generated for some configurations. generated for some configurations.
* Phaser: fixed coarse mixer frequency configuration * Phaser: fixed coarse mixer frequency configuration
@ -33,7 +37,7 @@ Highlights:
* New hardware support: * New hardware support:
- Phaser, a quad channel 1GS/s RF generator card with dual IQ upconverter and dual 5MS/s - Phaser, a quad channel 1GS/s RF generator card with dual IQ upconverter and dual 5MS/s
ADC and FPGA. ADC and FPGA.
- Zynq SoC core devices, enabling kernels to run on 1 GHz CPU core with a floating-point - Zynq SoC core device (ZC706), enabling kernels to run on 1 GHz CPU core with a floating-point
unit for faster computations. This currently requires an external unit for faster computations. This currently requires an external
repository (https://git.m-labs.hk/m-labs/artiq-zynq). repository (https://git.m-labs.hk/m-labs/artiq-zynq).
- Mirny 4-channel wide-band PLL/VCO-based microwave frequency synthesiser - Mirny 4-channel wide-band PLL/VCO-based microwave frequency synthesiser