From 299bc1cb7e6569744ef51f3efa01bc07d204254a Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 27 Jul 2015 20:46:44 +0800
Subject: [PATCH] kc705: output divided-by-2 RTIO clock

---
 soc/targets/artiq_kc705.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py
index 4677ada33..ffa61f76c 100644
--- a/soc/targets/artiq_kc705.py
+++ b/soc/targets/artiq_kc705.py
@@ -60,6 +60,10 @@ class _RTIOCRG(Module, AutoCSR):
             MultiReg(pll_locked, self._pll_locked.status)
         ]
 
+        # 62.5MHz when using internal RTIO clock
+        ext_clkout = platform.request("user_sma_gpio_p")
+        self.sync.rtio += ext_clkout.eq(~ext_clkout)
+
 
 class _NIST_QCx(MiniSoC, AMPSoC):
     csr_map = {