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urukul: make STA reading robust, add io_rst(), clean up

This commit is contained in:
Robert Jördens 2018-01-03 18:29:39 +00:00
parent cef40eef43
commit 28a3ee7e61
1 changed files with 11 additions and 3 deletions
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14
artiq/coredevice/urukul.py
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@ -113,6 +113,7 @@ class CPLD:
@kernel @kernel
def sta_read(self): def sta_read(self):
self.cfg_write(self.cfg_reg) # to latch STA
self.bus.set_config_mu(_SPI_CONFIG, _SPIT_CFG_WR, _SPIT_CFG_RD) self.bus.set_config_mu(_SPI_CONFIG, _SPIT_CFG_WR, _SPIT_CFG_RD)
self.bus.set_xfer(CS_CFG, 0, 24) self.bus.set_xfer(CS_CFG, 0, 24)
self.bus.write(self.cfg_reg << 8) self.bus.write(self.cfg_reg << 8)
@ -121,18 +122,25 @@ class CPLD:
@kernel @kernel
def init(self, clk_sel=0, sync_sel=0): def init(self, clk_sel=0, sync_sel=0):
t = now_mu()
cfg = urukul_cfg(rf_sw=0, led=0, profile=0, att_le=0, cfg = urukul_cfg(rf_sw=0, led=0, profile=0, att_le=0,
io_update=0, mask_nu=0, clk_sel=clk_sel, io_update=0, mask_nu=0, clk_sel=clk_sel,
sync_sel=sync_sel, rst=0, io_rst=0) sync_sel=sync_sel, rst=0, io_rst=0)
self.cfg_write(cfg | (1 << CFG_RST)) self.cfg_write(cfg | (1 << CFG_RST))
delay(100*us)
self.cfg_write(cfg) self.cfg_write(cfg)
proto_rev = urukul_sta_proto_rev(self.sta_read()) proto_rev = urukul_sta_proto_rev(self.sta_read())
if proto_rev != STA_PROTO_REV_MATCH: if proto_rev != STA_PROTO_REV_MATCH:
raise ValueError("Urukul proto_rev mismatch") raise ValueError("Urukul proto_rev mismatch")
at_mu(t)
delay(100*us) delay(100*us)
@kernel
def io_rst(self):
delay(1*us)
self.cfg_write(self.cfg_reg | (1 << CFG_IO_RST))
delay(1*us)
self.cfg_write(self.cfg_reg & ~(1 << CFG_IO_RST))
delay(1*us)
@kernel @kernel
def cfg_sw(self, sw, on): def cfg_sw(self, sw, on):
c = self.cfg_reg c = self.cfg_reg
@ -140,7 +148,7 @@ class CPLD:
c |= 1 << sw c |= 1 << sw
else: else:
c &= ~(1 << sw) c &= ~(1 << sw)
self.write_cfg(c) self.cfg_write(c)
@kernel @kernel
def set_att_mu(self, channel, att): def set_att_mu(self, channel, att):