forked from M-Labs/artiq
urukul: make STA reading robust, add io_rst(), clean up
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cef40eef43
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28a3ee7e61
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@ -113,6 +113,7 @@ class CPLD:
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@kernel
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def sta_read(self):
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self.cfg_write(self.cfg_reg) # to latch STA
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self.bus.set_config_mu(_SPI_CONFIG, _SPIT_CFG_WR, _SPIT_CFG_RD)
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self.bus.set_xfer(CS_CFG, 0, 24)
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self.bus.write(self.cfg_reg << 8)
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@ -121,18 +122,25 @@ class CPLD:
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@kernel
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def init(self, clk_sel=0, sync_sel=0):
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t = now_mu()
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cfg = urukul_cfg(rf_sw=0, led=0, profile=0, att_le=0,
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io_update=0, mask_nu=0, clk_sel=clk_sel,
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sync_sel=sync_sel, rst=0, io_rst=0)
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self.cfg_write(cfg | (1 << CFG_RST))
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delay(100*us)
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self.cfg_write(cfg)
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proto_rev = urukul_sta_proto_rev(self.sta_read())
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if proto_rev != STA_PROTO_REV_MATCH:
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raise ValueError("Urukul proto_rev mismatch")
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at_mu(t)
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delay(100*us)
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@kernel
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def io_rst(self):
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delay(1*us)
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self.cfg_write(self.cfg_reg | (1 << CFG_IO_RST))
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delay(1*us)
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self.cfg_write(self.cfg_reg & ~(1 << CFG_IO_RST))
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delay(1*us)
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@kernel
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def cfg_sw(self, sw, on):
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c = self.cfg_reg
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@ -140,7 +148,7 @@ class CPLD:
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c |= 1 << sw
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else:
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c &= ~(1 << sw)
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self.write_cfg(c)
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self.cfg_write(c)
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@kernel
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def set_att_mu(self, channel, att):
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