From 2881d5f00a1c5ec90c895227fb6767e5cb013163 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 2 Jul 2015 18:20:26 +0200 Subject: [PATCH] gateware: add RTIO clock generator --- artiq/gateware/rtio/phy/ttl_simple.py | 18 ++++++++++++++++++ doc/manual/fpga_board_ports.rst | 4 +++- soc/targets/artiq_kc705.py | 13 ++++++++++++- soc/targets/artiq_pipistrello.py | 6 +++++- 4 files changed, 38 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/rtio/phy/ttl_simple.py b/artiq/gateware/rtio/phy/ttl_simple.py index 3250a2659..8a5e6e432 100644 --- a/artiq/gateware/rtio/phy/ttl_simple.py +++ b/artiq/gateware/rtio/phy/ttl_simple.py @@ -75,3 +75,21 @@ class Inout(Module): ] self.probes += [i, ts.oe] + + +class ClockGen(Module): + def __init__(self, pad, ftw_width=16): + self.rtlink = rtlink.Interface( + rtlink.OInterface(ftw_width, suppress_nop=False)) + + # # # + + ftw = Signal(ftw_width) + acc = Signal(ftw_width) + self.sync.rio += If(self.rtlink.o.stb, ftw.eq(self.rtlink.o.data)) + self.sync.rio_phy += [ + acc.eq(acc + ftw), + # known phase on write: at rising edge + If(self.rtlink.o.stb, acc.eq(2**(ftw_width - 1))), + pad.eq(acc[-1]) + ] diff --git a/doc/manual/fpga_board_ports.rst b/doc/manual/fpga_board_ports.rst index 442c3e691..52bd8dffe 100644 --- a/doc/manual/fpga_board_ports.rst +++ b/doc/manual/fpga_board_ports.rst @@ -20,7 +20,9 @@ When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are +--------------+----------+------------+ | 1 | PMT1 | Input | +--------------+----------+------------+ -| 2-17 | TTL0-15 | Output | +| 2-16 | TTL0-14 | Output | ++--------------+----------+------------+ +| 17 | TTL15 | Clock | +--------------+----------+------------+ | 18 | EXT_LED | Output | +--------------+----------+------------+ diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py index d6631ef87..5ed077b5c 100644 --- a/soc/targets/artiq_kc705.py +++ b/soc/targets/artiq_kc705.py @@ -95,7 +95,7 @@ class NIST_QC1(_NIST_QCx): phy = ttl_simple.Inout(platform.request("pmt", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) - for i in range(16): + for i in range(15): phy = ttl_simple.Output(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) @@ -105,6 +105,10 @@ class NIST_QC1(_NIST_QCx): rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_constant("RTIO_TTL_COUNT", len(rtio_channels)) + phy = ttl_simple.ClockGen(platform.request("ttl", 15)) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels)) self.add_constant("DDS_CHANNEL_COUNT", 8) self.add_constant("DDS_AD9858") @@ -123,6 +127,9 @@ class NIST_QC2(_NIST_QCx): rtio_channels = [] for i in range(16): + if i == 14: + # TTL14 is for the clock generator + break if i % 4 == 3: phy = ttl_simple.Inout(platform.request("ttl", i)) self.submodules += phy @@ -137,6 +144,10 @@ class NIST_QC2(_NIST_QCx): rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_constant("RTIO_TTL_COUNT", len(rtio_channels)) + phy = ttl_simple.ClockGen(platform.request("ttl", 14)) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels)) self.add_constant("DDS_CHANNEL_COUNT", 11) self.add_constant("DDS_AD9914") diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py index b3bc058c3..3ad05a591 100644 --- a/soc/targets/artiq_pipistrello.py +++ b/soc/targets/artiq_pipistrello.py @@ -100,7 +100,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512, ofifo_depth=4)) - for i in range(16): + for i in range(15): phy = ttl_simple.Output(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256)) @@ -115,6 +115,10 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.add_constant("RTIO_TTL_COUNT", len(rtio_channels)) + phy = ttl_simple.ClockGen(platform.request("ttl", 15)) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels)) self.add_constant("DDS_CHANNEL_COUNT", 8) phy = dds.AD9858(platform.request("dds"), 8)