diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index ab76f9fa5..b83f08cfb 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -160,10 +160,9 @@ class Standalone(MiniSoC, AMPSoC):
         ]
 
         # RTM bitstream upload
-        # https://github.com/m-labs/artiq/issues/908#issuecomment-363650534
-        #rtm_fpga_cfg = platform.request("rtm_fpga_cfg")
-        #self.submodules.rtm_fpga_cfg = SlaveFPGA(rtm_fpga_cfg)
-        #self.csr_devices.append("rtm_fpga_cfg")
+        rtm_fpga_cfg = platform.request("rtm_fpga_cfg")
+        self.submodules.rtm_fpga_cfg = SlaveFPGA(rtm_fpga_cfg)
+        self.csr_devices.append("rtm_fpga_cfg")
 
         # AMC/RTM serwb
         serwb_pll = serwb.phy.SERWBPLL(125e6, 625e6, vco_div=2)