From 27e3c044ed28293b8f3df28cac4de7785e128c19 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Tue, 6 Sep 2022 14:32:57 +0000
Subject: [PATCH] fix dt computation

---
 artiq/coredevice/phaser.py        | 6 +++---
 artiq/gateware/rtio/phy/phaser.py | 9 +++++----
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/artiq/coredevice/phaser.py b/artiq/coredevice/phaser.py
index 472d8146f..18b1182d4 100644
--- a/artiq/coredevice/phaser.py
+++ b/artiq/coredevice/phaser.py
@@ -1469,13 +1469,13 @@ class Miqro:
         data[0] = window
         word = 0
         idx = 10
-        for i in range(len(profiles)):
-            if profiles[i] > 0x1f:
+        for profile in profiles:
+            if profile > 0x1f:
                 raise ValueError("profile out of bounds")
             if idx >= 30:
                 word += 1
                 idx = 0
-            data[word] |= (profiles[i] & 0x1f) << idx
+            data[word] |= profile << idx
             idx += 5
         return word
 
diff --git a/artiq/gateware/rtio/phy/phaser.py b/artiq/gateware/rtio/phy/phaser.py
index 1a1ced03d..4ff1e7d42 100644
--- a/artiq/gateware/rtio/phy/phaser.py
+++ b/artiq/gateware/rtio/phy/phaser.py
@@ -99,6 +99,7 @@ class MiqroChannel(Module):
         self.ack = Signal()
         regs = [Signal(30, reset_less=True) for _ in range(3)]
         dt = Signal(7, reset_less=True)
+        dt_frame = Signal(6, reset_less=True)
         stb = Signal()
         pulse = Cat(stb, dt, regs)
         assert len(self.pulse) >= len(pulse)
@@ -107,18 +108,18 @@ class MiqroChannel(Module):
             self.rtlink.o.busy.eq(stb & ~self.ack),
         ]
         self.sync.rtio += [
-            dt.eq(dt + 2),
+            dt_frame.eq(dt_frame + 1),
             If(self.ack,
-                dt[1:].eq(0),
-                stb.eq(0),
+                dt_frame.eq(0),
                 If(stb,
                     [r.eq(0) for r in regs],
                 ),
+                stb.eq(0),
             ),
             If(self.rtlink.o.stb,
                 Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data),
                 If(self.rtlink.o.address == 0,
-                    dt[0].eq(self.rtlink.o.fine_ts),
+                    dt.eq(Cat(self.rtlink.o.fine_ts, dt_frame)),
                     stb.eq(1),
                 ),
             ),