forked from M-Labs/artiq
rtio: expose full_ts_width instead of counter_width parameter
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@ -281,7 +281,7 @@ class _KernelCSRs(AutoCSR):
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class RTIO(Module):
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def __init__(self, channels, clk_freq, counter_width=63,
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def __init__(self, channels, clk_freq, full_ts_width=63,
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guard_io_cycles=20):
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data_width = max(rtlink.get_data_width(c.interface)
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for c in channels)
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@ -293,7 +293,7 @@ class RTIO(Module):
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# CSRs
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self.kcsrs = _KernelCSRs(bits_for(len(channels)-1),
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data_width, address_width,
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counter_width + fine_ts_width)
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full_ts_width)
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# Clocking/Reset
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# Create rsys and rio domains based on sys and rio
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@ -309,7 +309,7 @@ class RTIO(Module):
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self.kcsrs.reset.storage)
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# Managers
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self.submodules.counter = _RTIOCounter(counter_width)
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self.submodules.counter = _RTIOCounter(full_ts_width - fine_ts_width)
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i_datas, i_timestamps = [], []
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o_statuses, i_statuses = [], []
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