From 277e0385696e15b34203f12b29071b47ebdd361a Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sat, 4 Apr 2015 22:07:23 +0800
Subject: [PATCH] targets/kc705: add LED on RTIO

---
 examples/master/ddb.pyon   | 6 ++++++
 soc/targets/artiq_kc705.py | 4 +++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/examples/master/ddb.pyon b/examples/master/ddb.pyon
index b98f3c486..26c419701 100644
--- a/examples/master/ddb.pyon
+++ b/examples/master/ddb.pyon
@@ -43,6 +43,12 @@
         "class": "RTIOOut",
         "arguments": {"channel": 4}
     },
+    "led": {
+        "type": "local",
+        "module": "artiq.coredevice.rtio",
+        "class": "RTIOOut",
+        "arguments": {"channel": 18}
+    },
 
     "dds0": {
         "type": "local",
diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py
index e86813f26..64cbf3672 100644
--- a/soc/targets/artiq_kc705.py
+++ b/soc/targets/artiq_kc705.py
@@ -90,7 +90,9 @@ class _ARTIQSoCPeripherals(BaseSoC):
             platform.request("ttl_h_tx_en").eq(1)
         ]
         rtio_ins = [platform.request("pmt") for i in range(2)]
-        rtio_outs = [platform.request("ttl", i) for i in range(16)] + [fud]
+        rtio_outs = [platform.request("ttl", i) for i in range(16)]
+        rtio_outs.append(platform.request("user_led", 2))
+        rtio_outs.append(fud)
 
         self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys)
         self.submodules.rtiophy = rtio.phy.SimplePHY(