srenblad/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

ad9912: Fix typing problem on ad9912 (#1466)

Browse Source 
Closes #1463

FTW and phase word were ambiguously typed, resulting in failure to compile
This commit is contained in:
charlesbaynham 2020-06-16 19:17:22 +01:00 committed by GitHub
parent ce7e92a75e
commit 2429a266f6
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
artiq/coredevice/ad9912.py
View File

@ -1,5 +1,6 @@
from numpy import int32, int64
from artiq.language.types import TInt32, TInt64
from artiq.language.core import kernel, delay, portable
from artiq.language.units import ms, us, ns
from artiq.coredevice.ad9912_reg import *
@ -156,7 +157,7 @@ class AD9912:
self.cpld.io_update.pulse(10*ns)
@portable(flags={"fast-math"})
def frequency_to_ftw(self, frequency):
def frequency_to_ftw(self, frequency) -> TInt64:
"""Returns the 48-bit frequency tuning word corresponding to the given
frequency.
"""
@ -170,7 +171,7 @@ class AD9912:
return ftw/self.ftw_per_hz
@portable(flags={"fast-math"})
def turns_to_pow(self, phase):
def turns_to_pow(self, phase) -> TInt32:
"""Returns the 16-bit phase offset word corresponding to the given
phase.
"""