forked from M-Labs/artiq
ad9912: Fix typing problem on ad9912 (#1466)
Closes #1463 FTW and phase word were ambiguously typed, resulting in failure to compile
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@ -1,5 +1,6 @@
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from numpy import int32, int64
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from numpy import int32, int64
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from artiq.language.types import TInt32, TInt64
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from artiq.language.core import kernel, delay, portable
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from artiq.language.core import kernel, delay, portable
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from artiq.language.units import ms, us, ns
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from artiq.language.units import ms, us, ns
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from artiq.coredevice.ad9912_reg import *
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from artiq.coredevice.ad9912_reg import *
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@ -156,7 +157,7 @@ class AD9912:
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self.cpld.io_update.pulse(10*ns)
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self.cpld.io_update.pulse(10*ns)
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@portable(flags={"fast-math"})
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@portable(flags={"fast-math"})
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def frequency_to_ftw(self, frequency):
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def frequency_to_ftw(self, frequency) -> TInt64:
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"""Returns the 48-bit frequency tuning word corresponding to the given
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"""Returns the 48-bit frequency tuning word corresponding to the given
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frequency.
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frequency.
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"""
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"""
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@ -170,7 +171,7 @@ class AD9912:
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return ftw/self.ftw_per_hz
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return ftw/self.ftw_per_hz
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@portable(flags={"fast-math"})
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@portable(flags={"fast-math"})
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def turns_to_pow(self, phase):
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def turns_to_pow(self, phase) -> TInt32:
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"""Returns the 16-bit phase offset word corresponding to the given
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"""Returns the 16-bit phase offset word corresponding to the given
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phase.
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phase.
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"""
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"""
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