forked from M-Labs/artiq
siphaser: support external reference for the freerunning 150MHz
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6796413a53
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@ -4,16 +4,17 @@ from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr import *
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# This code assumes 125MHz system clock and 150MHz RTIO frequency.
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# This code assumes 125/62.5MHz reference clock and 150MHz RTIO frequency.
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class SiPhaser7Series(Module, AutoCSR):
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class SiPhaser7Series(Module, AutoCSR):
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def __init__(self, si5324_clkin, si5324_clkout_fabric):
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def __init__(self, si5324_clkin, si5324_clkout_fabric,
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ref_clk=None, ref_div2=False):
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self.switch_clocks = CSRStorage()
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self.switch_clocks = CSRStorage()
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self.phase_shift = CSR()
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self.phase_shift = CSR()
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self.phase_shift_done = CSRStatus(reset=1)
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self.phase_shift_done = CSRStatus(reset=1)
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self.sample_result = CSRStatus()
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self.sample_result = CSRStatus()
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# 125MHz system clock to 150MHz. VCO @ 625MHz.
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# 125MHz/62.5MHz reference clock to 150MHz. VCO @ 625MHz.
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# Used to provide a startup clock to the transceiver through the Si,
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# Used to provide a startup clock to the transceiver through the Si,
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# we do not use the crystal reference so that the PFD (f3) frequency
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# we do not use the crystal reference so that the PFD (f3) frequency
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# can be high.
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# can be high.
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@ -21,11 +22,12 @@ class SiPhaser7Series(Module, AutoCSR):
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mmcm_freerun_output = Signal()
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mmcm_freerun_output = Signal()
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self.specials += \
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self.specials += \
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Instance("MMCME2_BASE",
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=1e9/125e6,
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p_CLKIN1_PERIOD=16.0 if ref_div2 else 8.0,
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i_CLKIN1=ClockSignal("sys"),
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i_CLKIN1=ClockSignal("sys") if ref_clk is None else ref_clk,
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i_RST=ResetSignal("sys"),
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i_RST=ResetSignal("sys") if ref_clk is None else 0,
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p_CLKFBOUT_MULT_F=6.0, p_DIVCLK_DIVIDE=1,
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p_CLKFBOUT_MULT_F=12.0 if ref_div2 else 6.0,
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p_DIVCLK_DIVIDE=1,
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o_CLKFBOUT=mmcm_freerun_fb, i_CLKFBIN=mmcm_freerun_fb,
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o_CLKFBOUT=mmcm_freerun_fb, i_CLKFBIN=mmcm_freerun_fb,
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