diff --git a/artiq/coredevice/dds.py b/artiq/coredevice/dds.py
index 9332ac34c..3ef8cc8b5 100644
--- a/artiq/coredevice/dds.py
+++ b/artiq/coredevice/dds.py
@@ -156,24 +156,6 @@ class _DDSGeneric:
         timing margin."""
         dds_init(now_mu(), self.bus_channel, self.channel)
 
-    @kernel
-    def init_sync(self, sync_delay=0):
-        """Resets and initializes the DDS channel as well as configures
-        the AD9914 DDS for synchronisation. The synchronisation procedure
-        follows the steps outlined in the AN-1254 application note.
-
-        This needs to be done for each DDS channel before it can be used, and
-        it is recommended to use the startup kernel for this.
-
-        This function cannot be used in a batch; the correct way of
-        initializing multiple DDS channels is to call this function
-        sequentially with a delay between the calls. 10ms provides a good
-        timing margin.
-
-        :param sync_delay: integer from 0 to 0x3f that sets value of
-        SYNC_OUT (bits 3-5) and SYNC_IN (bits 0-2) delay ADJ bits."""
-        dds_init_sync(now_mu(), self.bus_channel, self.channel, sync_delay)
-
     @kernel
     def set_phase_mode(self, phase_mode):
         """Sets the phase mode of the DDS channel. Supported phase modes are:
@@ -236,3 +218,21 @@ class AD9914(_DDSGeneric):
     """Driver for AD9914 DDS chips. See ``_DDSGeneric`` for a description
     of the functionality."""
     pow_width = 16
+
+    @kernel
+    def init_sync(self, sync_delay=0):
+        """Resets and initializes the DDS channel as well as configures
+        the AD9914 DDS for synchronisation. The synchronisation procedure
+        follows the steps outlined in the AN-1254 application note.
+
+        This needs to be done for each DDS channel before it can be used, and
+        it is recommended to use the startup kernel for this.
+
+        This function cannot be used in a batch; the correct way of
+        initializing multiple DDS channels is to call this function
+        sequentially with a delay between the calls. 10ms provides a good
+        timing margin.
+
+        :param sync_delay: integer from 0 to 0x3f that sets value of
+        SYNC_OUT (bits 3-5) and SYNC_IN (bits 0-2) delay ADJ bits."""
+        dds_init_sync(now_mu(), self.bus_channel, self.channel, sync_delay)