forked from M-Labs/artiq
kc705: use misoc clock for false path
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@ -149,7 +149,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.rtio_crg.cd_rtio.clk.attr.add("keep")
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.rtio.cd_rsys.clk,
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self.crg.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
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