From 22ab62324c1c4eb2d810c163d2e02a41045d10fb Mon Sep 17 00:00:00 2001 From: David Nadlinger Date: Sun, 17 Sep 2023 00:48:42 +0100 Subject: [PATCH] gateware/targets/kasli: Set DRTIO_ROLE in {Master, Satellite}Base These were introduced in 82bd913f63e3, and for Kasli only set from the JSON description in the *Generic subclasses. Not all firmware is built through that API, however, e.g. the CI system at the University of Oxford. The missing attribute breaks artiq.build_soc. --- artiq/gateware/targets/kasli.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 6312170c9..ce9944a53 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -317,6 +317,7 @@ class MasterBase(MiniSoC, AMPSoC): self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO_ROUTING"] = None + self.config["DRTIO_ROLE"] = "master" rtio_clk_period = 1e9/rtio_clk_freq gtp = self.gt_drtio.gtps[0] @@ -565,6 +566,7 @@ class SatelliteBase(BaseSoC, AMPSoC): self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO_ROUTING"] = None + self.config["DRTIO_ROLE"] = "satellite" self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.add_csr_group("drtiorep", drtiorep_csr_group)