forked from M-Labs/artiq
drtio: full stack unittest
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f763b519f4
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@ -6,6 +6,7 @@ from migen import *
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from artiq.gateware.drtio import *
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from artiq.gateware.drtio import *
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from artiq.gateware import rtio
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.coredevice.exceptions import *
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class DummyTransceiverPair:
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class DummyTransceiverPair:
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@ -36,15 +37,21 @@ class DummyRXSynchronizer:
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class DUT(Module):
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class DUT(Module):
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def __init__(self, nwords):
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def __init__(self, nwords):
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self.ttl = Signal()
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self.ttl0 = Signal()
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self.ttl1 = Signal()
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self.transceivers = DummyTransceiverPair(nwords)
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self.transceivers = DummyTransceiverPair(nwords)
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self.submodules.master = DRTIOMaster(self.transceivers.alice)
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self.submodules.master = DRTIOMaster(self.transceivers.alice)
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rx_synchronizer = DummyRXSynchronizer()
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rx_synchronizer = DummyRXSynchronizer()
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self.submodules.phy = ttl_simple.Output(self.ttl)
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self.submodules.phy0 = ttl_simple.Output(self.ttl0)
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self.submodules.phy1 = ttl_simple.Output(self.ttl1)
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rtio_channels = [
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rtio.Channel.from_phy(self.phy0),
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rtio.Channel.from_phy(self.phy1)
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]
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self.submodules.satellite = DRTIOSatellite(
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self.submodules.satellite = DRTIOSatellite(
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self.transceivers.bob, rx_synchronizer, [rtio.Channel.from_phy(self.phy)])
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self.transceivers.bob, rx_synchronizer, rtio_channels)
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class TestFullStack(unittest.TestCase):
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class TestFullStack(unittest.TestCase):
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@ -52,36 +59,79 @@ class TestFullStack(unittest.TestCase):
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dut = DUT(2)
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dut = DUT(2)
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kcsrs = dut.master.rt_controller.kcsrs
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kcsrs = dut.master.rt_controller.kcsrs
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def get_fifo_space():
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now = 0
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def delay(dt):
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nonlocal now
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now += dt
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def get_fifo_space(channel):
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yield from kcsrs.chan_sel.write(channel)
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yield from kcsrs.o_get_fifo_space.write(1)
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yield from kcsrs.o_get_fifo_space.write(1)
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yield
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yield
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while (yield from kcsrs.o_status.read()) & 1:
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while (yield from kcsrs.o_status.read()) & 1:
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yield
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yield
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return (yield from kcsrs.o_dbg_fifo_space.read())
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return (yield from kcsrs.o_dbg_fifo_space.read())
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def test():
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def write(channel, data):
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print((yield from get_fifo_space()))
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yield from kcsrs.chan_sel.write(channel)
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yield from kcsrs.o_timestamp.write(550)
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yield from kcsrs.o_timestamp.write(now)
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yield from kcsrs.o_data.write(1)
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yield from kcsrs.o_data.write(data)
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yield from kcsrs.o_we.write(1)
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yield from kcsrs.o_we.write(1)
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yield
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yield
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status = 1
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status = 1
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while status:
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while status:
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status = yield from kcsrs.o_status.read()
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status = yield from kcsrs.o_status.read()
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print("status after write:", status)
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if status & 2:
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yield from kcsrs.o_underflow_reset.write(1)
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raise RTIOUnderflow
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if status & 4:
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yield from kcsrs.o_sequence_error_reset.write(1)
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raise RTIOSequenceError
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yield
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yield
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yield from kcsrs.o_timestamp.write(600)
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yield from kcsrs.o_data.write(0)
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yield from kcsrs.o_we.write(1)
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yield
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status = 1
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while status:
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status = yield from kcsrs.o_status.read()
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print("status after write:", status)
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yield
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for i in range(40):
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yield
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#print((yield from get_fifo_space()))
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run_simulation(dut, test(),
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def test():
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yield from get_fifo_space(0)
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yield from get_fifo_space(1)
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with self.assertRaises(RTIOUnderflow):
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yield from write(0, 0)
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delay(200*8)
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yield from write(0, 1)
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delay(5*8)
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yield from write(0, 0)
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yield from write(1, 1)
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delay(6*8)
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yield from write(1, 0)
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delay(-200*8)
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with self.assertRaises(RTIOSequenceError):
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yield from write(0, 1)
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delay(200*8)
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for _ in range(50):
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yield
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ttl_changes = []
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@passive
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def check_ttls():
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cycle = 0
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old_ttls = [0, 0]
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while True:
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ttls = [(yield dut.ttl0), (yield dut.ttl1)]
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for n, (old_ttl, ttl) in enumerate(zip(old_ttls, ttls)):
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if ttl != old_ttl:
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ttl_changes.append((cycle, n))
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old_ttls = ttls
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yield
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cycle += 1
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run_simulation(dut,
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{"sys": test(), "rtio": check_ttls()},
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{"sys": 8, "rtio": 5, "rtio_rx": 5, "rio": 5, "rio_phy": 5}, vcd_name="foo.vcd")
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{"sys": 8, "rtio": 5, "rtio_rx": 5, "rio": 5, "rio_phy": 5}, vcd_name="foo.vcd")
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self.assertEqual(ttl_changes, [
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(203, 0),
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(208, 0),
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(208, 1),
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(214, 1)
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])
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