From 21a1c6de3ff78f56a6034c9d934f3f29aa117c54 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 16 Oct 2019 17:53:40 +0800 Subject: [PATCH] sayma: use SFP0 for DRTIO master --- artiq/gateware/targets/sayma_amc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 82b53c817..44300653d 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -361,10 +361,10 @@ class Master(MiniSoC, AMPSoC): self.config["SI5324_AS_SYNTHESIZER"] = None self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) - self.comb += platform.request("sfp_tx_disable", 1).eq(0) + self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("cdr_clk_clean", 0), - data_pads=[platform.request("sfp", 1)] + + data_pads=[platform.request("sfp", 0)] + # 6 and not 8 to work around Vivado bug (Xilinx CR 1020646) [platform.request("rtm_gth", i) for i in range(6)], sys_clk_freq=self.clk_freq,