From 212892d92f4fcb1c46823f86e1ed3401e73b7f89 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 26 Sep 2018 10:13:33 +0800 Subject: [PATCH] style --- artiq/gateware/targets/kasli.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 9c37c2220..cbe9645cc 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -27,8 +27,8 @@ from artiq.build_soc import * class _RTIOCRG(Module, AutoCSR): def __init__(self, platform): - self._pll_reset = CSRStorage(reset=1) - self._pll_locked = CSRStatus() + self.pll_reset = CSRStorage(reset=1) + self.pll_locked = CSRStatus() self.clock_domains.cd_rtio = ClockDomain() self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True) @@ -60,7 +60,7 @@ class _RTIOCRG(Module, AutoCSR): # VCO @ 1GHz when using 125MHz input p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1, i_CLKFBIN=self.cd_rtio.clk, - i_RST=self._pll_reset.storage, + i_RST=self.pll_reset.storage, o_CLKFBOUT=rtio_clk, @@ -70,7 +70,7 @@ class _RTIOCRG(Module, AutoCSR): Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk), AsyncResetSynchronizer(self.cd_rtio, ~pll_locked), - MultiReg(pll_locked, self._pll_locked.status) + MultiReg(pll_locked, self.pll_locked.status) ]