forked from M-Labs/artiq
serwb: replace valid/ready with stb/ack
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@ -33,16 +33,16 @@ class SERWBCore(Module):
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packetizer.source.connect(tx_fifo.sink),
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tx_fifo.source.connect(scrambler.sink),
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If(phy.init.ready,
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If(scrambler.source.valid,
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If(scrambler.source.stb,
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phy.serdes.tx_k.eq(scrambler.source.k),
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phy.serdes.tx_d.eq(scrambler.source.d)
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),
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scrambler.source.ready.eq(phy.serdes.tx_ce)
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scrambler.source.ack.eq(phy.serdes.tx_ce)
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),
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# phy --> core
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If(phy.init.ready,
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descrambler.sink.valid.eq(phy.serdes.rx_ce),
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descrambler.sink.stb.eq(phy.serdes.rx_ce),
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descrambler.sink.k.eq(phy.serdes.rx_k),
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descrambler.sink.d.eq(phy.serdes.rx_d)
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),
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