forked from M-Labs/artiq
kasli: default to hardware v2
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35f1814235
commit
1f2182d4c7
@ -197,7 +197,7 @@ class SUServo(StandaloneBase):
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"""
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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hw_rev = "v2.0"
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StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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@ -588,7 +588,7 @@ class SatelliteBase(BaseSoC):
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class Master(MasterBase):
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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hw_rev = "v2.0"
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MasterBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.rtio_channels = []
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@ -611,7 +611,7 @@ class Master(MasterBase):
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class Satellite(SatelliteBase):
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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hw_rev = "v2.0"
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SatelliteBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.rtio_channels = []
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