forked from M-Labs/artiq
gateware/amp: use new ModuleTransformer API
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@ -33,7 +33,7 @@ class KernelCPU(Module):
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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if isinstance(platform.toolchain, XilinxVivadoToolchain):
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if isinstance(platform.toolchain, XilinxVivadoToolchain):
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from migen.fhdl.simplify import FullMemoryWE
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from migen.fhdl.simplify import FullMemoryWE
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self.submodules.wishbone2lasmi = FullMemoryWE(
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self.submodules.wishbone2lasmi = FullMemoryWE()(
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WB2LASMI(l2_size//4, lasmim))
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WB2LASMI(l2_size//4, lasmim))
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else:
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else:
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self.submodules.wishbone2lasmi = WB2LASMI(l2_size//4, lasmim)
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self.submodules.wishbone2lasmi = WB2LASMI(l2_size//4, lasmim)
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