diff --git a/artiq/gateware/targets/sayma_amc_standalone.py b/artiq/gateware/targets/sayma_amc_standalone.py
index 1c732281d..7a4de3d3c 100755
--- a/artiq/gateware/targets/sayma_amc_standalone.py
+++ b/artiq/gateware/targets/sayma_amc_standalone.py
@@ -168,7 +168,7 @@ class Standalone(MiniSoC, AMPSoC):
             serwb_phy_amc.serdes.cd_serwb_serdes.clk,
             serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk)
 
-        serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave")
+        serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave", with_scrambling=True)
         self.submodules += serwb_core
         self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
 
diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py
index df9206dc5..0632592b1 100755
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@@ -159,7 +159,7 @@ class SaymaRTM(Module):
             serwb_phy_rtm.serdes.cd_serwb_serdes.clk,
             serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk)
 
-        serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master")
+        serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master", with_scrambling=True)
         self.submodules += serwb_core
 
         # process CSR devices and connect them to serwb