forked from M-Labs/artiq
rtio: handle input timeout in gateware
The information passed by the runtime will be used by the DRTIO core to poll the remote side appropriately.
This commit is contained in:
parent
4f94709e9f
commit
1e6a33b586
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@ -4,13 +4,14 @@ use board::csr;
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use ::send;
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use kernel_proto::*;
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pub const RTIO_O_STATUS_FULL: u32 = 1;
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pub const RTIO_O_STATUS_WAIT: u32 = 1;
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pub const RTIO_O_STATUS_UNDERFLOW: u32 = 2;
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pub const RTIO_O_STATUS_SEQUENCE_ERROR: u32 = 4;
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pub const RTIO_O_STATUS_COLLISION: u32 = 8;
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pub const RTIO_O_STATUS_BUSY: u32 = 16;
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pub const RTIO_I_STATUS_EMPTY: u32 = 1;
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pub const RTIO_I_STATUS_WAIT_EVENT: u32 = 1;
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pub const RTIO_I_STATUS_OVERFLOW: u32 = 2;
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pub const RTIO_I_STATUS_WAIT_STATUS: u32 = 4;
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pub extern fn init() {
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send(&RtioInitRequest);
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@ -38,8 +39,8 @@ pub unsafe fn rtio_i_data_read(offset: usize) -> u32 {
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#[inline(never)]
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unsafe fn process_exceptional_status(timestamp: i64, channel: i32, status: u32) {
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if status & RTIO_O_STATUS_FULL != 0 {
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while csr::rtio::o_status_read() & RTIO_O_STATUS_FULL != 0 {}
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if status & RTIO_O_STATUS_WAIT != 0 {
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while csr::rtio::o_status_read() & RTIO_O_STATUS_WAIT != 0 {}
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}
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if status & RTIO_O_STATUS_UNDERFLOW != 0 {
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csr::rtio::o_underflow_reset_write(1);
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@ -70,7 +71,7 @@ unsafe fn process_exceptional_status(timestamp: i64, channel: i32, status: u32)
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pub extern fn output(timestamp: i64, channel: i32, addr: i32, data: i32) {
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unsafe {
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csr::rtio::chan_sel_write(channel as u32);
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csr::rtio::o_timestamp_write(timestamp as u64);
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csr::rtio::timestamp_write(timestamp as u64);
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csr::rtio::o_address_write(addr as u32);
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rtio_o_data_write(0, data as u32);
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csr::rtio::o_we_write(1);
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@ -84,7 +85,7 @@ pub extern fn output(timestamp: i64, channel: i32, addr: i32, data: i32) {
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pub extern fn output_wide(timestamp: i64, channel: i32, addr: i32, data: CSlice<i32>) {
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unsafe {
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csr::rtio::chan_sel_write(channel as u32);
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csr::rtio::o_timestamp_write(timestamp as u64);
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csr::rtio::timestamp_write(timestamp as u64);
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csr::rtio::o_address_write(addr as u32);
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for i in 0..data.len() {
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rtio_o_data_write(i, data[i] as u32)
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@ -100,22 +101,12 @@ pub extern fn output_wide(timestamp: i64, channel: i32, addr: i32, data: CSlice<
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pub extern fn input_timestamp(timeout: i64, channel: i32) -> u64 {
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unsafe {
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csr::rtio::chan_sel_write(channel as u32);
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let mut status;
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loop {
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status = csr::rtio::i_status_read();
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if status == 0 { break }
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csr::rtio::timestamp_write(timeout as u64);
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csr::rtio::i_request_write(1);
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if status & RTIO_I_STATUS_OVERFLOW != 0 {
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csr::rtio::i_overflow_reset_write(1);
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break
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}
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if get_counter() >= timeout {
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// check empty flag again to prevent race condition.
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// now we are sure that the time limit has been exceeded.
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let status = csr::rtio::i_status_read();
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if status & RTIO_I_STATUS_EMPTY != 0 { break }
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}
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// input FIFO is empty - keep waiting
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let mut status = RTIO_I_STATUS_WAIT_STATUS;
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while status & RTIO_I_STATUS_WAIT_STATUS != 0 {
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status = csr::rtio::i_status_read();
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}
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if status & RTIO_I_STATUS_OVERFLOW != 0 {
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@ -123,7 +114,7 @@ pub extern fn input_timestamp(timeout: i64, channel: i32) -> u64 {
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"RTIO input overflow on channel {0}",
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channel as i64, 0, 0);
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}
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if status & RTIO_I_STATUS_EMPTY != 0 {
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if status & RTIO_I_STATUS_WAIT_EVENT != 0 {
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return !0
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}
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@ -136,16 +127,19 @@ pub extern fn input_timestamp(timeout: i64, channel: i32) -> u64 {
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pub extern fn input_data(channel: i32) -> i32 {
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unsafe {
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csr::rtio::chan_sel_write(channel as u32);
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loop {
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let status = csr::rtio::i_status_read();
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if status == 0 { break }
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csr::rtio::timestamp_write(0xffffffff_ffffffff);
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csr::rtio::i_request_write(1);
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if status & RTIO_I_STATUS_OVERFLOW != 0 {
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csr::rtio::i_overflow_reset_write(1);
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raise!("RTIOOverflow",
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"RTIO input overflow on channel {0}",
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channel as i64, 0, 0);
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}
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let mut status = RTIO_I_STATUS_WAIT_STATUS;
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while status & RTIO_I_STATUS_WAIT_STATUS != 0 {
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status = csr::rtio::i_status_read();
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}
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if status & RTIO_I_STATUS_OVERFLOW != 0 {
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csr::rtio::i_overflow_reset_write(1);
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raise!("RTIOOverflow",
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"RTIO input overflow on channel {0}",
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channel as i64, 0, 0);
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}
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let data = rtio_i_data_read(0);
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@ -158,7 +152,7 @@ pub extern fn input_data(channel: i32) -> i32 {
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pub fn log(timestamp: i64, data: &[u8]) {
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unsafe {
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csr::rtio::chan_sel_write(csr::CONFIG_RTIO_LOG_CHANNEL);
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csr::rtio::o_timestamp_write(timestamp as u64);
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csr::rtio::timestamp_write(timestamp as u64);
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let mut word: u32 = 0;
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for i in 0..data.len() {
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@ -97,14 +97,14 @@ class RTController(Module):
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self.comb += [
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fifo_spaces.adr.eq(chan_sel),
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last_timestamps.adr.eq(chan_sel),
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last_timestamps.dat_w.eq(self.cri.o_timestamp),
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last_timestamps.dat_w.eq(self.cri.timestamp),
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rt_packets.write_channel.eq(chan_sel),
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rt_packets.write_address.eq(self.cri.o_address),
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rt_packets.write_data.eq(self.cri.o_data),
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If(rt_packets_fifo_request,
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rt_packets.write_timestamp.eq(0xffff000000000000)
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).Else(
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rt_packets.write_timestamp.eq(self.cri.o_timestamp)
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rt_packets.write_timestamp.eq(self.cri.timestamp)
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)
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]
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@ -137,8 +137,8 @@ class RTController(Module):
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self.submodules += timeout_counter
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# TODO: collision, replace, busy
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cond_sequence_error = self.cri.o_timestamp < last_timestamps.dat_r
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cond_underflow = ((self.cri.o_timestamp[fine_ts_width:]
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cond_sequence_error = self.cri.timestamp < last_timestamps.dat_r
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cond_underflow = ((self.cri.timestamp[fine_ts_width:]
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- self.csrs.underflow_margin.storage[fine_ts_width:]) < self.counter.value_sys)
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fsm.act("IDLE",
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@ -59,7 +59,7 @@ class MessageEncoder(Module, AutoCSR):
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input_output.rtio_counter.eq(cri.counter),
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If(cri.cmd == cri_commands["write"],
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input_output.message_type.eq(MessageType.output.value),
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input_output.timestamp.eq(cri.o_timestamp),
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input_output.timestamp.eq(cri.timestamp),
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input_output.data.eq(cri.o_data)
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).Else(
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input_output.message_type.eq(MessageType.input.value),
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@ -319,7 +319,7 @@ class Core(Module, AutoCSR):
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self.cd_rio_phy, cmd_reset_phy)
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# Managers
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self.submodules.counter = RTIOCounter(len(self.cri.o_timestamp) - fine_ts_width)
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self.submodules.counter = RTIOCounter(len(self.cri.timestamp) - fine_ts_width)
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i_datas, i_timestamps = [], []
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o_statuses, i_statuses = [], []
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@ -342,8 +342,8 @@ class Core(Module, AutoCSR):
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self.comb += o_manager.ev.data.eq(self.cri.o_data)
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if hasattr(o_manager.ev, "address"):
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self.comb += o_manager.ev.address.eq(self.cri.o_address)
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ts_shift = len(self.cri.o_timestamp) - len(o_manager.ev.timestamp)
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self.comb += o_manager.ev.timestamp.eq(self.cri.o_timestamp[ts_shift:])
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ts_shift = len(self.cri.timestamp) - len(o_manager.ev.timestamp)
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self.comb += o_manager.ev.timestamp.eq(self.cri.timestamp[ts_shift:])
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self.comb += o_manager.we.eq(selected & (self.cri.cmd == cri.commands["write"]))
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@ -395,17 +395,33 @@ class Core(Module, AutoCSR):
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If(i_manager.overflow,
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overflow.eq(1))
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]
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i_statuses.append(Cat(~i_manager.readable, overflow))
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i_statuses.append(Cat(i_manager.readable, overflow))
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else:
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i_datas.append(0)
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i_timestamps.append(0)
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i_statuses.append(0)
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i_status_raw = Signal(2)
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self.sync.rsys += i_status_raw.eq(Array(i_statuses)[sel])
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input_timeout = Signal.like(self.cri.timestamp)
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input_pending = Signal()
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self.sync.rsys += [
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If((self.cri.counter >= input_timeout) | (i_status_raw != 0),
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input_pending.eq(0)
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),
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If(self.cri.cmd == cri.commands["read_request"],
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input_timeout.eq(self.cri.timestamp),
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input_pending.eq(1)
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)
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]
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self.comb += [
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self.cri.i_data.eq(Array(i_datas)[sel]),
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self.cri.i_timestamp.eq(Array(i_timestamps)[sel]),
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self.cri.o_status.eq(Array(o_statuses)[sel]),
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self.cri.i_status.eq(Array(i_statuses)[sel])
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self.cri.i_status.eq(Cat(~i_status_raw[0], i_status_raw[1], input_pending)),
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self.cri.counter.eq(self.counter.value_sys << fine_ts_width)
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]
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self.comb += self.cri.counter.eq(self.counter.value_sys << fine_ts_width)
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@ -10,13 +10,17 @@ commands = {
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"nop": 0,
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"write": 1,
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"read": 2,
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# i_status should have the "wait for status" bit set until
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# an event is available, or timestamp is reached.
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"read_request": 2,
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# consume the read event
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"read": 3,
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"o_underflow_reset": 3,
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"o_sequence_error_reset": 4,
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"o_collision_reset": 5,
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"o_busy_reset": 6,
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"i_overflow_reset": 7
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"o_underflow_reset": 4,
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"o_sequence_error_reset": 5,
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"o_collision_reset": 6,
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"o_busy_reset": 7,
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"i_overflow_reset": 8
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}
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@ -27,10 +31,10 @@ layout = [
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("cmd", 4, DIR_M_TO_S),
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# 8 MSBs of chan_sel are used to select core
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("chan_sel", 24, DIR_M_TO_S),
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("timestamp", 64, DIR_M_TO_S),
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("o_data", 512, DIR_M_TO_S),
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("o_address", 16, DIR_M_TO_S),
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("o_timestamp", 64, DIR_M_TO_S),
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# o_status bits:
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# <0:wait> <1:underflow> <2:sequence_error> <3:collision> <4:busy>
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("o_status", 5, DIR_S_TO_M),
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@ -38,8 +42,8 @@ layout = [
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("i_data", 32, DIR_S_TO_M),
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("i_timestamp", 64, DIR_S_TO_M),
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# i_status bits:
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# <0:wait> <1:overflow>
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("i_status", 2, DIR_S_TO_M),
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# <0:wait for event> <1:overflow> <2:wait for status>
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("i_status", 3, DIR_S_TO_M),
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("counter", 64, DIR_S_TO_M)
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]
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@ -56,10 +60,11 @@ class KernelInitiator(Module, AutoCSR):
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self.arb_gnt = CSRStatus()
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self.chan_sel = CSRStorage(24)
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self.timestamp = CSRStorage(64)
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# writing timestamp set o_data to 0
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self.o_data = CSRStorage(512, write_from_dev=True)
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self.o_address = CSRStorage(16)
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self.o_timestamp = CSRStorage(64)
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self.o_we = CSR()
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self.o_status = CSRStatus(5)
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self.o_underflow_reset = CSR()
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@ -69,8 +74,9 @@ class KernelInitiator(Module, AutoCSR):
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self.i_data = CSRStatus(32)
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self.i_timestamp = CSRStatus(64)
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self.i_request = CSR()
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self.i_re = CSR()
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self.i_status = CSRStatus(2)
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self.i_status = CSRStatus(3)
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self.i_overflow_reset = CSR()
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self.counter = CSRStatus(64)
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@ -88,6 +94,7 @@ class KernelInitiator(Module, AutoCSR):
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self.cri.cmd.eq(commands["nop"]),
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If(self.o_we.re, self.cri.cmd.eq(commands["write"])),
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If(self.i_request.re, self.cri.cmd.eq(commands["read_request"])),
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If(self.i_re.re, self.cri.cmd.eq(commands["read"])),
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If(self.o_underflow_reset.re, self.cri.cmd.eq(commands["o_underflow_reset"])),
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If(self.o_sequence_error_reset.re, self.cri.cmd.eq(commands["o_sequence_error_reset"])),
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@ -96,10 +103,10 @@ class KernelInitiator(Module, AutoCSR):
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If(self.i_overflow_reset.re, self.cri.cmd.eq(commands["i_overflow_reset"])),
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self.cri.chan_sel.eq(self.chan_sel.storage),
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self.cri.timestamp.eq(self.timestamp.storage),
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self.cri.o_data.eq(self.o_data.storage),
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self.cri.o_address.eq(self.o_address.storage),
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self.cri.o_timestamp.eq(self.o_timestamp.storage),
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self.o_status.status.eq(self.cri.o_status),
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self.i_data.status.eq(self.cri.i_data),
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@ -107,7 +114,7 @@ class KernelInitiator(Module, AutoCSR):
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self.i_status.status.eq(self.cri.i_status),
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self.o_data.dat_w.eq(0),
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self.o_data.we.eq(self.o_timestamp.re),
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self.o_data.we.eq(self.timestamp.re),
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]
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self.sync += If(self.counter_update.re, self.counter.status.eq(self.cri.counter))
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@ -279,7 +279,7 @@ class CRIMaster(Module, AutoCSR):
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self.comb += [
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self.cri.chan_sel.eq(self.sink.channel),
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self.cri.o_timestamp.eq(self.sink.timestamp),
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self.cri.timestamp.eq(self.sink.timestamp),
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self.cri.o_address.eq(self.sink.address),
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self.cri.o_data.eq(self.sink.data)
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]
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@ -112,7 +112,7 @@ class TestFullStack(unittest.TestCase):
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def write(channel, data):
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yield from kcsrs.chan_sel.write(channel)
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yield from kcsrs.o_timestamp.write(now)
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yield from kcsrs.timestamp.write(now)
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yield from kcsrs.o_data.write(data)
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yield from kcsrs.o_we.write(1)
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yield
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@ -79,7 +79,7 @@ class TestDMA(unittest.TestCase):
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pass
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elif cmd == cri.commands["write"]:
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channel = yield dut_cri.chan_sel
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timestamp = yield dut_cri.o_timestamp
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timestamp = yield dut_cri.timestamp
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address = yield dut_cri.o_address
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data = yield dut_cri.o_data
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received.append((channel, timestamp, address, data))
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