forked from M-Labs/artiq
firmware: Fix Si5324 initialisation for satellites
Commit 740543d4e2
had unintentionally broken DRTIO
satellites, as si5324::setup is also used there. This
imports setup_si5324_as_synthesizer() from artiq-zynq,
where the input selection was already explicitly done.
GitHub: Fixes #2028.
This commit is contained in:
parent
ce57d6c346
commit
1db3a42ad7
@ -214,11 +214,9 @@ pub fn bypass(input: Input) -> Result<()> {
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Ok(())
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Ok(())
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}
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}
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pub fn setup(settings: &FrequencySettings, ext_input: Input) -> Result<()> {
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pub fn setup(settings: &FrequencySettings, input: Input) -> Result<()> {
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let s = map_frequency_settings(settings)?;
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let s = map_frequency_settings(settings)?;
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// FREE_RUN=1 routes XA/XB to CKIN2.
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let input = if settings.crystal_ref { Input::Ckin2 } else { ext_input };
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let cksel_reg = match input {
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let cksel_reg = match input {
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Input::Ckin1 => 0b00,
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Input::Ckin1 => 0b00,
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Input::Ckin2 => 0b01,
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Input::Ckin2 => 0b01,
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@ -130,9 +130,10 @@ const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin2;
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#[cfg(si5324_as_synthesizer)]
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#[cfg(si5324_as_synthesizer)]
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fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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let si5324_settings = match cfg {
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let (si5324_settings, si5324_ref_input) = match cfg {
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RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
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RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
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info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
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info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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si5324::FrequencySettings {
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n1_hs : 10,
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n1_hs : 10,
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nc1_ls : 4,
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nc1_ls : 4,
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@ -142,10 +143,13 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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n32 : 6,
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n32 : 6,
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bwsel : 4,
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bwsel : 4,
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crystal_ref: false
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crystal_ref: false
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}
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},
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SI5324_EXT_INPUT
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)
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},
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},
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RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
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RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
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info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
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info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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si5324::FrequencySettings {
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n1_hs : 10,
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n1_hs : 10,
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nc1_ls : 4,
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nc1_ls : 4,
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@ -155,10 +159,13 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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n32 : 52,
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n32 : 52,
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bwsel : 4,
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bwsel : 4,
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crystal_ref: false
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crystal_ref: false
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}
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},
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SI5324_EXT_INPUT
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)
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},
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},
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RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
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RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
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info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
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info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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si5324::FrequencySettings {
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n1_hs : 5,
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n1_hs : 5,
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nc1_ls : 8,
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nc1_ls : 8,
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@ -168,10 +175,13 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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n32 : 63,
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n32 : 63,
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bwsel : 4,
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bwsel : 4,
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crystal_ref: false
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crystal_ref: false
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}
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},
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SI5324_EXT_INPUT
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)
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},
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},
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RtioClock::Int_150 => { // 150MHz output, from crystal
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RtioClock::Int_150 => { // 150MHz output, from crystal
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info!("using internal 150MHz RTIO clock");
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info!("using internal 150MHz RTIO clock");
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(
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si5324::FrequencySettings {
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si5324::FrequencySettings {
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n1_hs : 9,
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n1_hs : 9,
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nc1_ls : 4,
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nc1_ls : 4,
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@ -181,10 +191,13 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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n32 : 7139,
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n32 : 7139,
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bwsel : 3,
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bwsel : 3,
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crystal_ref: true
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crystal_ref: true
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}
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},
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},
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RtioClock::Int_100 => { // 100MHz output, from crystal. Also used as reference for Sayma HMC830.
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si5324::Input::Ckin2
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)
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},
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RtioClock::Int_100 => { // 100MHz output, from crystal
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info!("using internal 100MHz RTIO clock");
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info!("using internal 100MHz RTIO clock");
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(
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si5324::FrequencySettings {
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si5324::FrequencySettings {
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n1_hs : 9,
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n1_hs : 9,
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nc1_ls : 6,
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nc1_ls : 6,
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@ -194,10 +207,13 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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n32 : 7139,
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n32 : 7139,
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bwsel : 3,
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bwsel : 3,
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crystal_ref: true
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crystal_ref: true
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}
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},
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si5324::Input::Ckin2
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)
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},
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},
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RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz
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RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz
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info!("using internal 125MHz RTIO clock");
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info!("using internal 125MHz RTIO clock");
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(
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si5324::FrequencySettings {
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si5324::FrequencySettings {
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n1_hs : 10,
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n1_hs : 10,
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nc1_ls : 4,
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nc1_ls : 4,
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@ -207,10 +223,13 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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n32 : 4565,
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n32 : 4565,
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bwsel : 4,
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bwsel : 4,
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crystal_ref: true
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crystal_ref: true
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}
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},
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}
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si5324::Input::Ckin2
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)
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},
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_ => { // 125MHz output like above, default (if chosen option is not supported)
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_ => { // 125MHz output like above, default (if chosen option is not supported)
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warn!("rtio_clock setting '{:?}' is not supported. Falling back to default internal 125MHz RTIO clock.", cfg);
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warn!("rtio_clock setting '{:?}' is not supported. Falling back to default internal 125MHz RTIO clock.", cfg);
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(
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si5324::FrequencySettings {
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si5324::FrequencySettings {
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n1_hs : 10,
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n1_hs : 10,
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nc1_ls : 4,
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nc1_ls : 4,
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@ -220,10 +239,12 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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n32 : 4565,
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n32 : 4565,
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bwsel : 4,
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bwsel : 4,
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crystal_ref: true
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crystal_ref: true
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}
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},
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si5324::Input::Ckin2
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)
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}
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}
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};
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};
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si5324::setup(&si5324_settings, SI5324_EXT_INPUT).expect("cannot initialize Si5324");
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si5324::setup(&si5324_settings, si5324_ref_input).expect("cannot initialize Si5324");
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}
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}
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pub fn init() {
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pub fn init() {
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