firmware: make DAC initialization failures non-fatal

This allows using RTMs with one broken DAC for development.

artiq/firmware/libboard_artiq/ad9154.rs

@@ -720,25 +720,31 @@ fn dac_sysref_cfg(dacno: u8, phase: u16) {
     hmc7043::cfg_dac_sysref(dacno, phase);
 }
 
-pub fn init() -> Result<(), &'static str> {
+fn init_dac(dacno: u8) -> Result<(), &'static str> {
+    let dacno = dacno as u8;
+    // Reset the DAC, detect and configure it
+    dac_reset(dacno);
+    dac_detect(dacno)?;
+    dac_cfg_retry(dacno)?;
+    // Run the PRBS, STPL and SYSREF scan tests
+    dac_prbs(dacno)?;
+    dac_stpl(dacno, 4, 2)?;
+    dac_sysref_scan(dacno);
+    // Set SYSREF phase and reconfigure the DAC
+    dac_sysref_cfg(dacno, 88);
+    dac_cfg_retry(dacno)?;
+    Ok(())
+}
+
+pub fn init() {
     // Release the JESD clock domain reset late, as we need to
     // set up clock chips before.
     jesd_unreset();
 
     for dacno in 0..csr::AD9154.len() {
-        let dacno = dacno as u8;
+        match init_dac(dacno as u8) {
-        // Reset the DAC, detect and configure it
+            Ok(_) => (),
-        dac_reset(dacno);
+            Err(e) => error!("failed to initialize AD9154-{}: {}", dacno, e)
-        dac_detect(dacno)?;
+        }
-        dac_cfg_retry(dacno)?;
-        // Run the PRBS, STPL and SYSREF scan tests
-        dac_prbs(dacno)?;
-        dac_stpl(dacno, 4, 2)?;
-        dac_sysref_scan(dacno);
-        // Set SYSREF phase and reconfigure the DAC
-        dac_sysref_cfg(dacno, 88);
-        dac_cfg_retry(dacno)?;
     }
-
-    Ok(())
 }

artiq/firmware/runtime/main.rs

@@ -109,7 +109,7 @@ fn startup() {
     /* must be the first SPI init because of HMC830 SPI mode selection */
     board_artiq::hmc830_7043::init().expect("cannot initialize HMC830/7043");
     #[cfg(has_ad9154)]
-    board_artiq::ad9154::init().expect("cannot initialize AD9154");
+    board_artiq::ad9154::init();
     #[cfg(has_allaki_atts)]
     board_artiq::hmc542::program_all(8/*=4dB*/);