forked from M-Labs/artiq
rtio/sed: make ON payload layout configurable, add latency function
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@ -1,6 +1,9 @@
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from migen import *
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__all__ = ["latency", "OutputNetwork"]
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# Based on: https://github.com/Bekbolatov/SortingNetworks/blob/master/src/main/js/gr.js
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def boms_get_partner(n, l, p):
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if p == 1:
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@ -34,21 +37,17 @@ def boms_steps_pairs(lane_count):
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return steps
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def layout_rtio_payload(fine_ts_width):
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return [
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("channel", 24),
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("fine_ts", fine_ts_width),
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("address", 16),
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("data", 512),
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]
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def latency(lane_count):
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d = log2_int(lane_count)
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return sum(l for l in range(1, d+1))
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def layout_node_data(seqn_width, fine_ts_width):
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def layout_node_data(seqn_width, layout_payload):
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return [
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("valid", 1),
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("seqn", seqn_width),
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("replace_occured", 1),
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("payload", layout_rtio_payload(fine_ts_width))
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("payload", layout_payload)
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]
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@ -57,14 +56,14 @@ def cmp_wrap(a, b):
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class OutputNetwork(Module):
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def __init__(self, lane_count, seqn_width, fine_ts_width):
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self.input = [Record(layout_node_data(seqn_width, fine_ts_width))
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def __init__(self, lane_count, seqn_width, layout_payload):
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self.input = [Record(layout_node_data(seqn_width, layout_payload))
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for _ in range(lane_count)]
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self.output = None
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step_input = self.input
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for step in boms_steps_pairs(lane_count):
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step_output = [Record(layout_node_data(seqn_width, fine_ts_width))
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step_output = [Record(layout_node_data(seqn_width, layout_payload))
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for _ in range(lane_count)]
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for node1, node2 in step:
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@ -9,7 +9,13 @@ LANE_COUNT = 8
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def simulate(input_events):
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dut = output_network.OutputNetwork(LANE_COUNT, LANE_COUNT*4, 3)
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layout_payload = [
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("channel", 8),
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("fine_ts", 3),
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("address", 16),
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("data", 512),
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]
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dut = output_network.OutputNetwork(LANE_COUNT, LANE_COUNT*4, layout_payload)
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output = []
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def gen():
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yield
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@ -21,7 +27,7 @@ def simulate(input_events):
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yield
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for n in range(len(input_events)):
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yield dut.input[n].valid.eq(0)
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for i in range(6):
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for i in range(output_network.latency(LANE_COUNT)):
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yield
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for x in range(LANE_COUNT):
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if (yield dut.output[x].valid):
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