From 1d081ed6c26b8866df7cddebfce888a91aa48662 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 12 Mar 2018 23:41:19 +0800 Subject: [PATCH] drtio: print diagnostic info on satellite write underflow (#947) --- artiq/firmware/satman/main.rs | 15 +++++++++++++-- artiq/gateware/drtio/rt_errors_satellite.py | 17 +++++++++++++++-- artiq/gateware/test/drtio/test_full_stack.py | 6 +++++- 3 files changed, 33 insertions(+), 5 deletions(-) diff --git a/artiq/firmware/satman/main.rs b/artiq/firmware/satman/main.rs index 19ab75bcc..bb20c5450 100644 --- a/artiq/firmware/satman/main.rs +++ b/artiq/firmware/satman/main.rs @@ -177,7 +177,6 @@ fn process_errors() { let errors; unsafe { errors = (csr::DRTIO[0].protocol_error_read)(); - (csr::DRTIO[0].protocol_error_write)(errors); } if errors & 1 != 0 { error!("received packet of an unknown type"); @@ -186,11 +185,23 @@ fn process_errors() { error!("received truncated packet"); } if errors & 4 != 0 { - error!("write underflow"); + let channel; + let timestamp_event; + let timestamp_counter; + unsafe { + channel = (csr::DRTIO[0].underflow_channel_read)(); + timestamp_event = (csr::DRTIO[0].underflow_timestamp_event_read)() as i64; + timestamp_counter = (csr::DRTIO[0].underflow_timestamp_counter_read)() as i64; + } + error!("write underflow, channel={}, timestamp={}, counter={}, slack={}", + channel, timestamp_event, timestamp_counter, timestamp_event-timestamp_counter); } if errors & 8 != 0 { error!("write overflow"); } + unsafe { + (csr::DRTIO[0].protocol_error_write)(errors); + } } #[cfg(rtio_frequency = "150.0")] diff --git a/artiq/gateware/drtio/rt_errors_satellite.py b/artiq/gateware/drtio/rt_errors_satellite.py index 743b5e031..8d563a3dc 100644 --- a/artiq/gateware/drtio/rt_errors_satellite.py +++ b/artiq/gateware/drtio/rt_errors_satellite.py @@ -9,6 +9,10 @@ from artiq.gateware.rtio.cdc import BlindTransfer class RTErrorsSatellite(Module, AutoCSR): def __init__(self, rt_packet, outputs): self.protocol_error = CSR(4) + self.underflow_channel = CSRStatus(16) + self.underflow_timestamp_event = CSRStatus(64) + self.underflow_timestamp_counter = CSRStatus(64) + self.rtio_error = CSR(3) self.sequence_error_channel = CSRStatus(16) self.collision_channel = CSRStatus(16) @@ -49,16 +53,25 @@ class RTErrorsSatellite(Module, AutoCSR): # internal ARTIQ bugs. underflow = Signal() overflow = Signal() + underflow_error_cri = Signal(16+64+64) + underflow_error_csr = Signal(16+64+64) self.comb += [ underflow.eq(outputs.cri.o_status[1]), - overflow.eq(outputs.cri.o_status[0]) + overflow.eq(outputs.cri.o_status[0]), + underflow_error_cri.eq(Cat(outputs.cri.chan_sel[:16], + outputs.cri.timestamp, + outputs.cri.counter)), + Cat(self.underflow_channel.status, + self.underflow_timestamp_event.status, + self.underflow_timestamp_counter.status).eq(underflow_error_csr) ] error_csr(self.protocol_error, (rt_packet.unknown_packet_type, False, None, None), (rt_packet.packet_truncated, False, None, None), - (underflow, True, None, None), + (underflow, True, underflow_error_cri, underflow_error_csr), (overflow, True, None, None) ) + error_csr(self.rtio_error, (outputs.sequence_error, False, outputs.sequence_error_channel, self.sequence_error_channel.status), diff --git a/artiq/gateware/test/drtio/test_full_stack.py b/artiq/gateware/test/drtio/test_full_stack.py index 82b0d1c79..feade41d4 100644 --- a/artiq/gateware/test/drtio/test_full_stack.py +++ b/artiq/gateware/test/drtio/test_full_stack.py @@ -222,11 +222,15 @@ class TestFullStack(unittest.TestCase): self.assertEqual(errors, 0) yield from csrs.underflow_margin.write(0) tb.delay(100) - yield from tb.write(0, 1) + yield from tb.write(42, 1) for i in range(12): yield errors = yield from saterr.protocol_error.read() + underflow_channel = yield from saterr.underflow_channel.read() + underflow_timestamp_event = yield from saterr.underflow_timestamp_event.read() self.assertEqual(errors, 4) # write underflow + self.assertEqual(underflow_channel, 42) + self.assertEqual(underflow_timestamp_event, 100) yield from saterr.protocol_error.write(errors) yield errors = yield from saterr.protocol_error.read()