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rtio/sed/Gates: fix fine_ts_width computation

This commit is contained in:
Sebastien Bourdeauducq 2017-09-16 15:09:21 +08:00
parent 30e7765a2e
commit 1cfe90b1d9
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/rtio/sed/gates.py
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@ -13,8 +13,8 @@ class Gates(Module):
self.output = [Record(layouts.output_network_node(seqn_width, layout_output_network_payload)) self.output = [Record(layouts.output_network_node(seqn_width, layout_output_network_payload))
for _ in range(lane_count)] for _ in range(lane_count)]
if hasattr(self.output[0], "fine_ts"): if hasattr(self.output[0].payload, "fine_ts"):
fine_ts_width = len(self.output[0].fine_ts) fine_ts_width = len(self.output[0].payload.fine_ts)
else: else:
fine_ts_width = 0 fine_ts_width = 0