From 1cfe90b1d94e044d7ab1837f307ebe7a9ace5711 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 16 Sep 2017 15:09:21 +0800 Subject: [PATCH] rtio/sed/Gates: fix fine_ts_width computation --- artiq/gateware/rtio/sed/gates.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/rtio/sed/gates.py b/artiq/gateware/rtio/sed/gates.py index 3475c71a1..7ed460d0c 100644 --- a/artiq/gateware/rtio/sed/gates.py +++ b/artiq/gateware/rtio/sed/gates.py @@ -13,8 +13,8 @@ class Gates(Module): self.output = [Record(layouts.output_network_node(seqn_width, layout_output_network_payload)) for _ in range(lane_count)] - if hasattr(self.output[0], "fine_ts"): - fine_ts_width = len(self.output[0].fine_ts) + if hasattr(self.output[0].payload, "fine_ts"): + fine_ts_width = len(self.output[0].payload.fine_ts) else: fine_ts_width = 0