From 1c96797de59e9c0c20abb94e9c665df348ea4f15 Mon Sep 17 00:00:00 2001
From: Marius Weber <marius.weber@physics.ox.ac.uk>
Date: Fri, 2 Apr 2021 14:32:42 +0100
Subject: [PATCH] Phaser upconverter: Follow datasheet procedure for VCO
 calibration (close #1643)

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
---
 artiq/coredevice/phaser.py    | 29 +++++++++++++++++++++++++++++
 artiq/coredevice/trf372017.py |  9 +++++----
 2 files changed, 34 insertions(+), 4 deletions(-)

diff --git a/artiq/coredevice/phaser.py b/artiq/coredevice/phaser.py
index e165ba2f2..e122c75c1 100644
--- a/artiq/coredevice/phaser.py
+++ b/artiq/coredevice/phaser.py
@@ -323,6 +323,7 @@ class Phaser:
             delay(.2*ms)
             for data in channel.trf_mmap:
                 channel.trf_write(data)
+            channel.cal_trf_vco()
 
             delay(2*ms)  # lock
             if not (self.get_sta() & (PHASER_STA_TRF0_LD << ch)):
@@ -331,6 +332,7 @@ class Phaser:
             if channel.trf_read(0) & 0x1000:
                 raise ValueError("TRF R_SAT_ERR")
             delay(.1*ms)
+            channel.en_trf_out()
 
         # enable dac tx
         self.set_cfg(clk_sel=self.clk_sel)
@@ -689,6 +691,7 @@ class PhaserChannel:
         self.phaser = phaser
         self.index = index
         self.trf_mmap = TRF372017(trf).get_mmap()
+
         self.oscillator = [PhaserOscillator(self, osc) for osc in range(5)]
 
     @kernel
@@ -891,6 +894,32 @@ class PhaserChannel:
         return self.trf_write(0x00000008 | (cnt_mux_sel << 27),
                               readback=True)
 
+    @kernel
+    def cal_trf_vco(self):
+        """Start calibration of the upconverter (hardware variant) VCO.
+
+        TRF outputs should be disabled during VCO calibration.
+        """
+        self.trf_write(self.trf_mmap[1] | (1 << 31))
+
+    @kernel
+    def en_trf_out(self, rf=1, lo=0):
+        """Enable the rf/lo outputs of the upconverter (hardware variant).
+
+        :param rf: 1 to enable RF output, 0 to disable
+        :param lo: 1 to enable LO output, 0 to disable
+        """
+        data = self.trf_read(0xc)
+        delay(0.1 * ms)
+        # set RF and LO output bits
+        data = data | (1 << 12) | (1 << 13) | (1 << 14)
+        # clear to enable output
+        if rf == 1:
+            data = data ^ (1 << 14)
+        if lo == 1:
+            data = data ^ ((1 << 12) | (1 << 13))
+        self.trf_write(data)
+
 
 class PhaserOscillator:
     """Phaser IQ channel oscillator (NCO/DDS).
diff --git a/artiq/coredevice/trf372017.py b/artiq/coredevice/trf372017.py
index e4f114847..d6edb7313 100644
--- a/artiq/coredevice/trf372017.py
+++ b/artiq/coredevice/trf372017.py
@@ -17,7 +17,7 @@ class TRF372017:
     vco_sel = 2  # 2b
     vcosel_mode = 0
     cal_acc = 0b00  # 2b
-    en_cal = 1
+    en_cal = 0  # leave at 0 - calibration is performed in `Phaser.init()`
 
     nfrac = 0  # 25b
 
@@ -27,9 +27,9 @@ class TRF372017:
     pwd_vcomux = 0
     pwd_div124 = 0
     pwd_presc = 0
-    pwd_out_buff = 1
-    pwd_lo_div = 1
-    pwd_tx_div = 0
+    pwd_out_buff = 1  # leave at 1 - only enable outputs after calibration
+    pwd_lo_div = 1  # leave at 1 - only enable outputs after calibration
+    pwd_tx_div = 1  # leave at 1 - only enable outputs after calibration
     pwd_bb_vcm = 0
     pwd_dc_off = 0
     en_extvco = 0
@@ -84,6 +84,7 @@ class TRF372017:
             setattr(self, key, value)
 
     def get_mmap(self):
+        """Memory map for TRF372017"""
         mmap = []
         mmap.append(
             0x9 |