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examples: Add edge counters to kasli_tester variant 

This enables test_edge_counter on the CI system.
This commit is contained in:
David Nadlinger 2018-12-16 20:33:15 +00:00
parent 67a6882e91
commit 1c71ae636a
2 changed files with 46 additions and 38 deletions
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79
artiq/examples/kasli_tester/device_db.py
View File

@ -47,51 +47,57 @@ for i in range(8):
"class": "TTLInOut" if i < 4 else "TTLOut", "class": "TTLInOut" if i < 4 else "TTLOut",
"arguments": {"channel": i}, "arguments": {"channel": i},
} }
device_db["ttl{}_counter".format(i)] = {
"type": "local",
"module": "artiq.coredevice.edge_counter",
"class": "EdgeCounter",
"arguments": {"channel": 8 + i},
}
# Urukul (EEM1) starting at RTIO channel 8 # Urukul (EEM1) starting at RTIO channel 12
device_db.update( device_db.update(
spi_urukul0={ spi_urukul0={
"type": "local", "type": "local",
"module": "artiq.coredevice.spi2", "module": "artiq.coredevice.spi2",
"class": "SPIMaster", "class": "SPIMaster",
"arguments": {"channel": 8} "arguments": {"channel": 12}
}, },
ttl_urukul0_sync={ ttl_urukul0_sync={
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLClockGen", "class": "TTLClockGen",
"arguments": {"channel": 9, "acc_width": 4} "arguments": {"channel": 13, "acc_width": 4}
}, },
ttl_urukul0_io_update={ ttl_urukul0_io_update={
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 10} "arguments": {"channel": 14}
}, },
ttl_urukul0_sw0={ ttl_urukul0_sw0={
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 11} "arguments": {"channel": 15}
}, },
ttl_urukul0_sw1={ ttl_urukul0_sw1={
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 12} "arguments": {"channel": 16}
}, },
ttl_urukul0_sw2={ ttl_urukul0_sw2={
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 13} "arguments": {"channel": 17}
}, },
ttl_urukul0_sw3={ ttl_urukul0_sw3={
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 14} "arguments": {"channel": 18}
}, },
urukul0_cpld={ urukul0_cpld={
"type": "local", "type": "local",
@ -121,24 +127,24 @@ for i in range(4):
} }
# Sampler (EEM3) starting at RTIO channel 15 # Sampler (EEM3) starting at RTIO channel 19
device_db["spi_sampler0_adc"] = { device_db["spi_sampler0_adc"] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.spi2", "module": "artiq.coredevice.spi2",
"class": "SPIMaster", "class": "SPIMaster",
"arguments": {"channel": 15} "arguments": {"channel": 19}
} }
device_db["spi_sampler0_pgia"] = { device_db["spi_sampler0_pgia"] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.spi2", "module": "artiq.coredevice.spi2",
"class": "SPIMaster", "class": "SPIMaster",
"arguments": {"channel": 16} "arguments": {"channel": 20}
} }
device_db["spi_sampler0_cnv"] = { device_db["spi_sampler0_cnv"] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 17}, "arguments": {"channel": 21},
} }
device_db["sampler0"] = { device_db["sampler0"] = {
"type": "local", "type": "local",
@ -152,24 +158,24 @@ device_db["sampler0"] = {
} }
# Zotino (EEM4) starting at RTIO channel 18 # Zotino (EEM4) starting at RTIO channel 22
device_db["spi_zotino0"] = { device_db["spi_zotino0"] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.spi2", "module": "artiq.coredevice.spi2",
"class": "SPIMaster", "class": "SPIMaster",
"arguments": {"channel": 18} "arguments": {"channel": 22}
} }
device_db["ttl_zotino0_ldac"] = { device_db["ttl_zotino0_ldac"] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 19} "arguments": {"channel": 23}
} }
device_db["ttl_zotino0_clr"] = { device_db["ttl_zotino0_clr"] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 20} "arguments": {"channel": 24}
} }
device_db["zotino0"] = { device_db["zotino0"] = {
"type": "local", "type": "local",
@ -183,34 +189,34 @@ device_db["zotino0"] = {
} }
# Grabber (EEM6) starting at RTIO channel 21 # Grabber (EEM6) starting at RTIO channel 25
device_db["grabber0"] = { device_db["grabber0"] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.grabber", "module": "artiq.coredevice.grabber",
"class": "Grabber", "class": "Grabber",
"arguments": {"channel_base": 21} "arguments": {"channel_base": 25}
} }
# Urukul (EEM7) starting at RTIO channel 23 # Urukul (EEM7) starting at RTIO channel 27
device_db.update( device_db.update(
spi_urukul1={ spi_urukul1={
"type": "local", "type": "local",
"module": "artiq.coredevice.spi2", "module": "artiq.coredevice.spi2",
"class": "SPIMaster", "class": "SPIMaster",
"arguments": {"channel": 23} "arguments": {"channel": 27}
}, },
ttl_urukul1_sync={ ttl_urukul1_sync={
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLClockGen", "class": "TTLClockGen",
"arguments": {"channel": 24, "acc_width": 4} "arguments": {"channel": 28, "acc_width": 4}
}, },
ttl_urukul1_io_update={ ttl_urukul1_io_update={
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 25} "arguments": {"channel": 29}
}, },
urukul1_cpld={ urukul1_cpld={
"type": "local", "type": "local",
@ -239,44 +245,44 @@ for i in range(4):
} }
# DIO (EEM8) starting at RTIO channel 26 # DIO (EEM8) starting at RTIO channel 30
for i in range(8): for i in range(8):
device_db["ttl" + str(8 + i)] = { device_db["ttl" + str(8 + i)] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 26 + i}, "arguments": {"channel": 30 + i},
} }
# DIO (EEM9) starting at RTIO channel 34 # DIO (EEM9) starting at RTIO channel 38
for i in range(8): for i in range(8):
device_db["ttl" + str(16 + i)] = { device_db["ttl" + str(16 + i)] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 34 + i}, "arguments": {"channel": 38 + i},
} }
# Sampler (EEM10) starting at RTIO channel 42 # Sampler (EEM10) starting at RTIO channel 46
device_db["spi_sampler1_adc"] = { device_db["spi_sampler1_adc"] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.spi2", "module": "artiq.coredevice.spi2",
"class": "SPIMaster", "class": "SPIMaster",
"arguments": {"channel": 42} "arguments": {"channel": 46}
} }
device_db["spi_sampler1_pgia"] = { device_db["spi_sampler1_pgia"] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.spi2", "module": "artiq.coredevice.spi2",
"class": "SPIMaster", "class": "SPIMaster",
"arguments": {"channel": 43} "arguments": {"channel": 47}
} }
device_db["spi_sampler1_cnv"] = { device_db["spi_sampler1_cnv"] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 44}, "arguments": {"channel": 48},
} }
device_db["sampler1"] = { device_db["sampler1"] = {
"type": "local", "type": "local",
@ -290,24 +296,24 @@ device_db["sampler1"] = {
} }
# Zotino (EEM11) starting at RTIO channel 45 # Zotino (EEM11) starting at RTIO channel 49
device_db["spi_zotino1"] = { device_db["spi_zotino1"] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.spi2", "module": "artiq.coredevice.spi2",
"class": "SPIMaster", "class": "SPIMaster",
"arguments": {"channel": 45} "arguments": {"channel": 49}
} }
device_db["ttl_zotino1_ldac"] = { device_db["ttl_zotino1_ldac"] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 46} "arguments": {"channel": 50}
} }
device_db["ttl_zotino1_clr"] = { device_db["ttl_zotino1_clr"] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 47} "arguments": {"channel": 51}
} }
device_db["zotino1"] = { device_db["zotino1"] = {
"type": "local", "type": "local",
@ -326,13 +332,13 @@ device_db.update(
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 48} "arguments": {"channel": 52}
}, },
led1={ led1={
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLOut", "class": "TTLOut",
"arguments": {"channel": 49} "arguments": {"channel": 53}
}, },
) )
@ -342,6 +348,7 @@ device_db.update(
loop_out="ttl4", loop_out="ttl4",
loop_in="ttl0", loop_in="ttl0",
loop_in_counter="ttl0_counter",
# Urukul CPLD with sync and io_update, IFC MODE 0b1000 # Urukul CPLD with sync and io_update, IFC MODE 0b1000
urukul_cpld="urukul0_cpld", urukul_cpld="urukul0_cpld",

5
artiq/gateware/targets/kasli.py
View File

@ -16,7 +16,7 @@ from misoc.integration.builder import builder_args, builder_argdict
from artiq.gateware.amp import AMPSoC from artiq.gateware.amp import AMPSoC
from artiq.gateware import rtio from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
from artiq.gateware import eem from artiq.gateware import eem
from artiq.gateware.drtio.transceiver import gtp_7series from artiq.gateware.drtio.transceiver import gtp_7series
from artiq.gateware.drtio.siphaser import SiPhaser7Series from artiq.gateware.drtio.siphaser import SiPhaser7Series
@ -737,7 +737,8 @@ class Tester(_StandaloneBase):
self.rtio_channels = [] self.rtio_channels = []
self.grabber_csr_group = [] self.grabber_csr_group = []
eem.DIO.add_std(self, 5, eem.DIO.add_std(self, 5,
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X) ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X,
edge_counter_cls=edge_counter.SimpleEdgeCounter)
eem.Urukul.add_std(self, 0, 1, ttl_serdes_7series.Output_8X, eem.Urukul.add_std(self, 0, 1, ttl_serdes_7series.Output_8X,
ttl_simple.ClockGen) ttl_simple.ClockGen)
eem.Sampler.add_std(self, 3, 2, ttl_serdes_7series.Output_8X) eem.Sampler.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)