forked from M-Labs/artiq
rtio: error recovery
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@ -8,8 +8,8 @@ from artiqlib.rtio.rbus import get_fine_ts_width
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class _RTIOBankO(Module):
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def __init__(self, rbus, counter_width, fine_ts_width,
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fifo_depth, counter_init):
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def __init__(self, rbus, counter, fine_ts_width, fifo_depth):
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counter_width = flen(counter)
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self.sel = Signal(max=len(rbus))
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self.timestamp = Signal(counter_width+fine_ts_width)
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self.value = Signal(2)
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@ -18,16 +18,13 @@ class _RTIOBankO(Module):
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self.replace = Signal()
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self.underflow = Signal()
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self.level = Signal(bits_for(fifo_depth))
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self.counter = Signal(counter_width, reset=counter_init)
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# # #
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self.sync += self.counter.eq(self.counter + 1)
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# detect underflows
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self.sync += \
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If((self.we & self.writable) | self.replace,
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If(self.timestamp[fine_ts_width:] < self.counter + 2,
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If(self.timestamp[fine_ts_width:] < counter + 2,
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self.underflow.eq(1))
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)
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@ -50,7 +47,7 @@ class _RTIOBankO(Module):
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# FIFO read
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self.comb += [
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chif.o_stb.eq(fifo.readable &
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(fifo.dout.timestamp[fine_ts_width:] == self.counter)),
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(fifo.dout.timestamp[fine_ts_width:] == counter)),
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chif.o_value.eq(fifo.dout.value),
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fifo.re.eq(chif.o_stb)
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]
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@ -66,7 +63,8 @@ class _RTIOBankO(Module):
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class _RTIOBankI(Module):
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def __init__(self, rbus, counter_width, fine_ts_width, fifo_depth):
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def __init__(self, rbus, counter, fine_ts_width, fifo_depth):
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counter_width = flen(counter)
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self.sel = Signal(max=len(rbus))
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self.timestamp = Signal(counter_width+fine_ts_width)
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self.value = Signal()
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@ -75,10 +73,7 @@ class _RTIOBankI(Module):
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self.overflow = Signal()
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self.pileup = Signal()
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###
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counter = Signal(counter_width)
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self.sync += counter.eq(counter + 1)
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# # #
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timestamps = []
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values = []
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@ -143,17 +138,30 @@ class RTIO(Module, AutoCSR):
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def __init__(self, phy, clk_freq, counter_width=32, ofifo_depth=64, ififo_depth=64):
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fine_ts_width = get_fine_ts_width(phy.rbus)
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# Counters
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reset_counter = Signal()
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o_counter = Signal(counter_width, reset=phy.loopback_latency)
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i_counter = Signal(counter_width)
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self.sync += \
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If(reset_counter,
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o_counter.eq(o_counter.reset),
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i_counter.eq(i_counter.reset)
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).Else(
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o_counter.eq(o_counter + 1),
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i_counter.eq(i_counter + 1)
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)
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# Submodules
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self.submodules.bank_o = InsertReset(_RTIOBankO(
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phy.rbus,
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counter_width, fine_ts_width, ofifo_depth,
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phy.loopback_latency))
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o_counter, fine_ts_width, ofifo_depth))
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self.submodules.bank_i = InsertReset(_RTIOBankI(
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phy.rbus,
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counter_width, fine_ts_width, ofifo_depth))
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i_counter, fine_ts_width, ofifo_depth))
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# CSRs
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self._r_reset = CSRStorage(reset=1)
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self._r_reset_logic = CSRStorage(reset=1)
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self._r_reset_counter = CSRStorage(reset=1)
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self._r_chan_sel = CSRStorage(flen(self.bank_o.sel))
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self._r_oe = CSR()
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@ -194,7 +202,7 @@ class RTIO(Module, AutoCSR):
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# Output/Gate
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self.comb += [
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self.bank_o.reset.eq(self._r_reset.storage),
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self.bank_o.reset.eq(self._r_reset_logic.storage),
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self.bank_o.sel.eq(self._r_chan_sel.storage),
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self.bank_o.timestamp.eq(self._r_o_timestamp.storage),
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self.bank_o.value.eq(self._r_o_value.storage),
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@ -207,7 +215,7 @@ class RTIO(Module, AutoCSR):
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# Input
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self.comb += [
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self.bank_i.reset.eq(self._r_reset.storage),
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self.bank_i.reset.eq(self._r_reset_logic.storage),
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self.bank_i.sel.eq(self._r_chan_sel.storage),
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self._r_i_timestamp.status.eq(self.bank_i.timestamp),
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self._r_i_value.status.eq(self.bank_i.value),
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@ -217,11 +225,12 @@ class RTIO(Module, AutoCSR):
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Cat(self.bank_i.overflow, self.bank_i.pileup))
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]
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# Counter
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# Counter access
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self.comb += reset_counter.eq(self._r_reset_counter.storage)
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self.sync += \
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If(self._r_counter_update.re,
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self._r_counter.status.eq(Cat(Replicate(0, fine_ts_width),
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self.bank_o.counter))
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o_counter))
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)
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# Frequency
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@ -31,10 +31,10 @@ static void fud(long long int fud_time)
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long long int fud_end_time;
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static long long int previous_fud_end_time;
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r = rtio_reset_read();
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r = rtio_reset_counter_read();
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if(r)
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previous_fud_end_time = 0;
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rtio_reset_write(0);
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rtio_reset_counter_write(0);
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rtio_chan_sel_write(RTIO_FUD_CHANNEL);
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if(fud_time < 0) {
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@ -52,12 +52,15 @@ static void fud(long long int fud_time)
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rtio_o_timestamp_write(fud_end_time);
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rtio_o_value_write(0);
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rtio_o_we_write(1);
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if(rtio_o_error_read())
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if(rtio_o_error_read()) {
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rtio_reset_logic_write(1);
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rtio_reset_logic_write(0);
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exception_raise(EID_RTIO_UNDERFLOW);
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}
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if(r) {
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fud_sync();
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rtio_reset_write(1);
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rtio_reset_counter_write(1);
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}
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}
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@ -110,6 +110,7 @@ int main(void)
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uart_init();
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puts("ARTIQ runtime built "__DATE__" "__TIME__"\n");
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rtio_init();
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dds_init();
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blink_led();
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corecom_serve(load_object, run_kernel);
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@ -5,7 +5,9 @@
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void rtio_init(void)
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{
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rtio_reset_write(1);
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rtio_reset_counter_write(1);
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rtio_reset_logic_write(1);
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rtio_reset_logic_write(0);
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}
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void rtio_oe(int channel, int oe)
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@ -16,14 +18,17 @@ void rtio_oe(int channel, int oe)
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void rtio_set(long long int timestamp, int channel, int value)
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{
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rtio_reset_write(0);
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rtio_reset_counter_write(0);
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rtio_chan_sel_write(channel);
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rtio_o_timestamp_write(timestamp);
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rtio_o_value_write(value);
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while(!rtio_o_writable_read());
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rtio_o_we_write(1);
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if(rtio_o_error_read())
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if(rtio_o_error_read()) {
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rtio_reset_logic_write(1);
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rtio_reset_logic_write(0);
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exception_raise(EID_RTIO_UNDERFLOW);
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}
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}
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void rtio_replace(long long int timestamp, int channel, int value)
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@ -32,8 +37,11 @@ void rtio_replace(long long int timestamp, int channel, int value)
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rtio_o_timestamp_write(timestamp);
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rtio_o_value_write(value);
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rtio_o_replace_write(1);
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if(rtio_o_error_read())
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if(rtio_o_error_read()) {
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rtio_reset_logic_write(1);
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rtio_reset_logic_write(0);
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exception_raise(EID_RTIO_UNDERFLOW);
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}
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}
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void rtio_sync(int channel)
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