forked from M-Labs/artiq
Gateware: si549 & WRPLL
ddmtd: add DDMTD and deglitcher wrpll: add helper clockdomain wrpll: add frequency counter wrpll: add skewtester wrpll: add gtx & main tag collection wrpll: add gtx & main tag eventmanager for interrupt si549: add i2c and adpll programmer
This commit is contained in:
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0
artiq/gateware/wrpll/__init__.py
Normal file
0
artiq/gateware/wrpll/__init__.py
Normal file
119
artiq/gateware/wrpll/ddmtd.py
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119
artiq/gateware/wrpll/ddmtd.py
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from migen import *
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from migen.genlib.cdc import PulseSynchronizer, MultiReg
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from misoc.interconnect.csr import *
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class DDMTDSampler(Module):
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def __init__(self, cd_ref, main_clk_se):
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self.ref_beating = Signal()
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self.main_beating = Signal()
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# # #
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ref_clk = Signal()
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self.specials +=[
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# ISERDESE2 can only be driven from fabric via IDELAYE2 (see UG471)
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Instance("IDELAYE2",
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p_DELAY_SRC="DATAIN",
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p_HIGH_PERFORMANCE_MODE="TRUE",
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p_REFCLK_FREQUENCY=208.3, # REFCLK frequency from IDELAYCTRL
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p_IDELAY_VALUE=0,
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i_DATAIN=cd_ref.clk,
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o_DATAOUT=ref_clk
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),
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Instance("ISERDESE2",
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p_IOBDELAY="IFD", # use DDLY as input
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p_DATA_RATE="SDR",
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p_DATA_WIDTH=2, # min is 2
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p_NUM_CE=1,
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i_DDLY=ref_clk,
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i_CE1=1,
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i_CLK=ClockSignal("helper"),
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i_CLKDIV=ClockSignal("helper"),
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o_Q1=self.ref_beating
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),
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Instance("ISERDESE2",
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p_DATA_RATE="SDR",
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p_DATA_WIDTH=2, # min is 2
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p_NUM_CE=1,
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i_D=main_clk_se,
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i_CE1=1,
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i_CLK=ClockSignal("helper"),
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i_CLKDIV=ClockSignal("helper"),
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o_Q1=self.main_beating,
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),
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]
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class DDMTDDeglitcherMedianEdge(Module):
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def __init__(self, counter, input_signal, stable_0_period=100, stable_1_period=100):
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self.tag = Signal(len(counter))
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self.detect = Signal()
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stable_0_counter = Signal(reset=stable_0_period - 1, max=stable_0_period)
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stable_1_counter = Signal(reset=stable_1_period - 1, max=stable_1_period)
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# # #
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# Based on CERN's median edge deglitcher FSM
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# https://white-rabbit.web.cern.ch/documents/Precise_time_and_frequency_transfer_in_a_White_Rabbit_network.pdf (p.72)
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fsm = ClockDomainsRenamer("helper")(FSM(reset_state="WAIT_STABLE_0"))
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self.submodules += fsm
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fsm.act("WAIT_STABLE_0",
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If(stable_0_counter != 0,
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NextValue(stable_0_counter, stable_0_counter - 1)
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).Else(
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NextValue(stable_0_counter, stable_0_period - 1),
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NextState("WAIT_EDGE")
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),
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If(input_signal,
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NextValue(stable_0_counter, stable_0_period - 1)
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),
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)
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fsm.act("WAIT_EDGE",
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If(input_signal,
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NextValue(self.tag, counter),
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NextState("GOT_EDGE")
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)
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)
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fsm.act("GOT_EDGE",
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If(stable_1_counter != 0,
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NextValue(stable_1_counter, stable_1_counter - 1)
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).Else(
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NextValue(stable_1_counter, stable_1_period - 1),
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self.detect.eq(1),
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NextState("WAIT_STABLE_0")
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),
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If(~input_signal,
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NextValue(self.tag, self.tag + 1),
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NextValue(stable_1_counter, stable_1_period - 1)
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),
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)
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class DDMTD(Module):
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def __init__(self, counter, input_signal):
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# in helper clock domain
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self.h_tag = Signal(len(counter))
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self.h_tag_update = Signal()
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# # #
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deglitcher = DDMTDDeglitcherMedianEdge(counter, input_signal)
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self.submodules += deglitcher
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self.sync.helper += [
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self.h_tag_update.eq(0),
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If(deglitcher.detect,
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self.h_tag_update.eq(1),
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self.h_tag.eq(deglitcher.tag)
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)
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]
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277
artiq/gateware/wrpll/si549.py
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277
artiq/gateware/wrpll/si549.py
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from migen import *
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from migen.genlib.fsm import *
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from misoc.interconnect.csr import *
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class I2CClockGen(Module):
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def __init__(self, width):
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self.load = Signal(width)
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self.clk2x = Signal()
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cnt = Signal.like(self.load)
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self.comb += [
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self.clk2x.eq(cnt == 0),
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]
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self.sync += [
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If(self.clk2x,
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cnt.eq(self.load),
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).Else(
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cnt.eq(cnt - 1),
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)
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]
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class I2CMasterMachine(Module):
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def __init__(self, clock_width):
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self.scl = Signal(reset=1)
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self.sda_o = Signal(reset=1)
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self.sda_i = Signal()
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self.submodules.cg = CEInserter()(I2CClockGen(clock_width))
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self.start = Signal()
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self.stop = Signal()
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self.write = Signal()
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self.ack = Signal()
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self.data = Signal(8)
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self.ready = Signal()
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# # #
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bits = Signal(4)
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data = Signal(8)
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fsm = CEInserter()(FSM("IDLE"))
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self.submodules += fsm
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fsm.act("IDLE",
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self.ready.eq(1),
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If(self.start,
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NextState("START0"),
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).Elif(self.stop,
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NextState("STOP0"),
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).Elif(self.write,
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NextValue(bits, 8),
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NextValue(data, self.data),
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NextState("WRITE0")
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)
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)
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fsm.act("START0",
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NextValue(self.scl, 1),
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NextState("START1")
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)
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fsm.act("START1",
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NextValue(self.sda_o, 0),
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NextState("IDLE")
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)
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fsm.act("STOP0",
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NextValue(self.scl, 0),
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NextState("STOP1")
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)
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fsm.act("STOP1",
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NextValue(self.sda_o, 0),
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NextState("STOP2")
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)
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fsm.act("STOP2",
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NextValue(self.scl, 1),
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NextState("STOP3")
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)
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fsm.act("STOP3",
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NextValue(self.sda_o, 1),
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NextState("IDLE")
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)
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fsm.act("WRITE0",
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NextValue(self.scl, 0),
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NextState("WRITE1")
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)
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fsm.act("WRITE1",
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If(bits == 0,
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NextValue(self.sda_o, 1),
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NextState("READACK0"),
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).Else(
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NextValue(self.sda_o, data[7]),
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NextState("WRITE2"),
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)
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)
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fsm.act("WRITE2",
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NextValue(self.scl, 1),
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NextValue(data[1:], data[:-1]),
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NextValue(bits, bits - 1),
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NextState("WRITE0"),
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)
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fsm.act("READACK0",
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NextValue(self.scl, 1),
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NextState("READACK1"),
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)
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fsm.act("READACK1",
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NextValue(self.ack, ~self.sda_i),
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NextState("IDLE")
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)
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run = Signal()
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idle = Signal()
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self.comb += [
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run.eq((self.start | self.stop | self.write) & self.ready),
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idle.eq(~run & fsm.ongoing("IDLE")),
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self.cg.ce.eq(~idle),
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fsm.ce.eq(run | self.cg.clk2x),
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]
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class ADPLLProgrammer(Module):
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def __init__(self):
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self.i2c_divider = Signal(16)
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self.i2c_address = Signal(7)
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self.adpll = Signal(24)
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self.stb = Signal()
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self.busy = Signal()
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self.nack = Signal()
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self.scl = Signal()
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self.sda_i = Signal()
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self.sda_o = Signal()
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# # #
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master = I2CMasterMachine(16)
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self.submodules += master
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self.comb += [
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master.cg.load.eq(self.i2c_divider),
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self.scl.eq(master.scl),
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master.sda_i.eq(self.sda_i),
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self.sda_o.eq(master.sda_o)
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]
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fsm = FSM()
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.stb,
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NextValue(self.nack, 0),
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NextState("START")
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)
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)
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fsm.act("START",
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master.start.eq(1),
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If(master.ready, NextState("DEVADDRESS"))
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)
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fsm.act("DEVADDRESS",
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master.data.eq(self.i2c_address << 1),
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master.write.eq(1),
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If(master.ready, NextState("REGADRESS"))
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)
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fsm.act("REGADRESS",
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master.data.eq(231),
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master.write.eq(1),
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If(master.ready,
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If(master.ack,
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NextState("DATA0")
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).Else(
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NextValue(self.nack, 1),
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NextState("STOP")
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)
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)
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)
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fsm.act("DATA0",
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master.data.eq(self.adpll[0:8]),
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master.write.eq(1),
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If(master.ready,
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If(master.ack,
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NextState("DATA1")
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).Else(
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NextValue(self.nack, 1),
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NextState("STOP")
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)
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)
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)
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fsm.act("DATA1",
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master.data.eq(self.adpll[8:16]),
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master.write.eq(1),
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If(master.ready,
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If(master.ack,
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NextState("DATA2")
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).Else(
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NextValue(self.nack, 1),
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NextState("STOP")
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)
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)
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)
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fsm.act("DATA2",
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master.data.eq(self.adpll[16:24]),
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master.write.eq(1),
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If(master.ready,
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If(~master.ack, NextValue(self.nack, 1)),
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NextState("STOP")
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)
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)
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fsm.act("STOP",
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master.stop.eq(1),
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If(master.ready,
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If(~master.ack, NextValue(self.nack, 1)),
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NextState("IDLE")
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)
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)
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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class Si549(Module, AutoCSR):
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def __init__(self, pads):
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self.i2c_divider = CSRStorage(16, reset=75)
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self.i2c_address = CSRStorage(7)
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self.adpll = CSRStorage(24)
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self.adpll_stb = CSR()
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self.adpll_busy = CSRStatus()
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self.nack = CSRStatus()
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self.bitbang_enable = CSRStorage()
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self.sda_oe = CSRStorage()
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self.sda_out = CSRStorage()
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self.sda_in = CSRStatus()
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self.scl_oe = CSRStorage()
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self.scl_out = CSRStorage()
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# # #
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self.submodules.programmer = ADPLLProgrammer()
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self.sync += self.programmer.stb.eq(self.adpll_stb.re)
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self.comb += [
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self.programmer.i2c_divider.eq(self.i2c_divider.storage),
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self.programmer.i2c_address.eq(self.i2c_address.storage),
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self.programmer.adpll.eq(self.adpll.storage),
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self.adpll_busy.status.eq(self.programmer.busy),
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self.nack.status.eq(self.programmer.nack)
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]
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# I2C with bitbang/gateware mode select
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sda_t = TSTriple(1)
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scl_t = TSTriple(1)
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self.specials += [
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sda_t.get_tristate(pads.sda),
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scl_t.get_tristate(pads.scl)
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]
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self.comb += [
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If(self.bitbang_enable.storage,
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sda_t.oe.eq(self.sda_oe.storage),
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sda_t.o.eq(self.sda_out.storage),
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self.sda_in.status.eq(sda_t.i),
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scl_t.oe.eq(self.scl_oe.storage),
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scl_t.o.eq(self.scl_out.storage)
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).Else(
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sda_t.oe.eq(~self.programmer.sda_o),
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sda_t.o.eq(0),
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self.programmer.sda_i.eq(sda_t.i),
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scl_t.oe.eq(~self.programmer.scl),
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scl_t.o.eq(0),
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)
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]
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173
artiq/gateware/wrpll/wrpll.py
Normal file
173
artiq/gateware/wrpll/wrpll.py
Normal file
@ -0,0 +1,173 @@
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from migen import *
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from migen.genlib.cdc import MultiReg, AsyncResetSynchronizer, PulseSynchronizer
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr_eventmanager import *
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from artiq.gateware.wrpll.ddmtd import DDMTDSampler, DDMTD
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from artiq.gateware.wrpll.si549 import Si549
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class FrequencyCounter(Module, AutoCSR):
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def __init__(self, domains, counter_width=24):
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self.update = CSR()
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self.busy = CSRStatus()
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counter_reset = Signal()
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counter_stb = Signal()
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timer = Signal(counter_width)
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# # #
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fsm = FSM()
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self.submodules += fsm
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fsm.act("IDLE",
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counter_reset.eq(1),
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If(self.update.re,
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NextValue(timer, 2**counter_width - 1),
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NextState("COUNTING")
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)
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)
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fsm.act("COUNTING",
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self.busy.status.eq(1),
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If(timer != 0,
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NextValue(timer, timer - 1)
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).Else(
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counter_stb.eq(1),
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NextState("IDLE")
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)
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)
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for domain in domains:
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name = "counter_" + domain
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counter_csr = CSRStatus(counter_width, name=name)
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setattr(self, name, counter_csr)
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divider = Signal(2)
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divided = Signal()
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divided_sys = Signal()
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divided_sys_r = Signal()
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divided_tick = Signal()
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counter = Signal(counter_width)
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# # #
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sync_domain = getattr(self.sync, domain)
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sync_domain +=[
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divider.eq(divider + 1),
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divided.eq(divider[-1])
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]
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self.specials += MultiReg(divided, divided_sys)
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self.sync += divided_sys_r.eq(divided_sys)
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self.comb += divided_tick.eq(divided_sys & ~divided_sys_r)
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self.sync += [
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If(counter_stb, counter_csr.status.eq(counter)),
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If(divided_tick, counter.eq(counter + 1)),
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If(counter_reset, counter.eq(0))
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]
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class SkewTester(Module, AutoCSR):
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def __init__(self, rx_synchronizer):
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self.error = CSR()
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# # #
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# The RX synchronizer is tested for setup/hold violations by feeding it a
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# toggling pattern and checking that the same toggling pattern comes out.
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toggle_in = Signal()
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self.sync.rtio_rx0 += toggle_in.eq(~toggle_in)
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toggle_out = rx_synchronizer.resync(toggle_in)
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toggle_out_expected = Signal()
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self.sync += toggle_out_expected.eq(~toggle_out)
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error = Signal()
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self.sync += [
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If(toggle_out != toggle_out_expected, error.eq(1)),
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If(self.error.re, error.eq(0))
|
||||
]
|
||||
self.specials += MultiReg(error, self.error.w)
|
||||
|
||||
|
||||
class WRPLL(Module, AutoCSR):
|
||||
def __init__(self, platform, cd_ref, main_clk_se, COUNTER_BIT=32):
|
||||
self.helper_reset = CSRStorage(reset=1)
|
||||
self.ref_tag = CSRStatus(COUNTER_BIT)
|
||||
self.main_tag = CSRStatus(COUNTER_BIT)
|
||||
|
||||
ddmtd_counter = Signal(COUNTER_BIT)
|
||||
|
||||
ref_tag_sys = Signal(COUNTER_BIT)
|
||||
main_tag_sys = Signal(COUNTER_BIT)
|
||||
ref_tag_stb_sys = Signal()
|
||||
main_tag_stb_sys = Signal()
|
||||
|
||||
# # #
|
||||
|
||||
self.submodules.main_dcxo = Si549(platform.request("ddmtd_main_dcxo_i2c"))
|
||||
self.submodules.helper_dcxo = Si549(platform.request("ddmtd_helper_dcxo_i2c"))
|
||||
|
||||
helper_dcxo_pads = platform.request("ddmtd_helper_clk")
|
||||
self.clock_domains.cd_helper = ClockDomain()
|
||||
self.specials += [
|
||||
Instance("IBUFGDS",
|
||||
i_I=helper_dcxo_pads.p, i_IB=helper_dcxo_pads.n,
|
||||
o_O=self.cd_helper.clk),
|
||||
AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage)
|
||||
]
|
||||
|
||||
self.submodules.frequency_counter = FrequencyCounter(["sys", cd_ref.name])
|
||||
|
||||
self.submodules.ddmtd_sampler = DDMTDSampler(cd_ref, main_clk_se)
|
||||
|
||||
self.sync.helper += ddmtd_counter.eq(ddmtd_counter + 1)
|
||||
self.submodules.ddmtd_ref = DDMTD(ddmtd_counter, self.ddmtd_sampler.ref_beating)
|
||||
self.submodules.ddmtd_main = DDMTD(ddmtd_counter, self.ddmtd_sampler.main_beating)
|
||||
|
||||
# DDMTD tags collection
|
||||
|
||||
self.specials += [
|
||||
MultiReg(self.ddmtd_ref.h_tag, ref_tag_sys),
|
||||
MultiReg(self.ddmtd_main.h_tag, main_tag_sys)
|
||||
]
|
||||
|
||||
ref_tag_stb_ps = PulseSynchronizer("helper", "sys")
|
||||
main_tag_stb_ps = PulseSynchronizer("helper", "sys")
|
||||
self.submodules += [
|
||||
ref_tag_stb_ps,
|
||||
main_tag_stb_ps
|
||||
]
|
||||
self.sync.helper += [
|
||||
ref_tag_stb_ps.i.eq(self.ddmtd_ref.h_tag_update),
|
||||
main_tag_stb_ps.i.eq(self.ddmtd_main.h_tag_update)
|
||||
]
|
||||
self.sync += [
|
||||
ref_tag_stb_sys.eq(ref_tag_stb_ps.o),
|
||||
main_tag_stb_sys.eq(main_tag_stb_ps.o)
|
||||
]
|
||||
|
||||
self.sync += [
|
||||
If(ref_tag_stb_sys,
|
||||
self.ref_tag.status.eq(ref_tag_sys),
|
||||
),
|
||||
If(main_tag_stb_sys,
|
||||
self.main_tag.status.eq(main_tag_sys)
|
||||
)
|
||||
]
|
||||
|
||||
# EventMangers for firmware interrupt
|
||||
|
||||
self.submodules.ref_tag_ev = EventManager()
|
||||
self.ref_tag_ev.stb = EventSourcePulse()
|
||||
self.ref_tag_ev.finalize()
|
||||
|
||||
self.submodules.main_tag_ev = EventManager()
|
||||
self.main_tag_ev.stb = EventSourcePulse()
|
||||
self.main_tag_ev.finalize()
|
||||
|
||||
self.sync += [
|
||||
self.ref_tag_ev.stb.trigger.eq(ref_tag_stb_sys),
|
||||
self.main_tag_ev.stb.trigger.eq(main_tag_stb_sys)
|
||||
]
|
||||
|
||||
self.submodules.ev = SharedIRQ(self.ref_tag_ev, self.main_tag_ev)
|
||||
Loading…
Reference in New Issue
Block a user