forked from M-Labs/artiq
drtio: integrate GTH transceiver for Sayma
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@ -6,6 +6,7 @@ from migen import *
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from migen.build.generic_platform import *
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from misoc.cores import spi as spi_csr
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from misoc.cores import gpio
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from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from misoc.targets.sayma_amc import MiniSoC
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@ -40,6 +41,7 @@ class Master(MiniSoC, AMPSoC):
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AMPSoC.__init__(self)
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platform = self.platform
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rtio_clk_freq = 150e6
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# Si5324 used as a free-running oscillator, to avoid dependency on RTM.
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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@ -55,7 +57,8 @@ class Master(MiniSoC, AMPSoC):
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clock_pads=platform.request("si5324_clkout"),
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tx_pads=[platform.request("sfp_tx")],
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rx_pads=[platform.request("sfp_rx")],
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sys_clk_freq=self.clk_freq)
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
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DRTIOMaster(self.transceiver.channels[0]))
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@ -67,12 +70,13 @@ class Master(MiniSoC, AMPSoC):
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
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platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
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platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.transceiver.txoutclk, self.transceiver.rxoutclk)
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rtio_clk_period = 1e9/rtio_clk_freq
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for gth in self.transceiver.gths:
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gth.txoutclk, gth.rxoutclk)
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rtio_channels = []
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for i in range(4):
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@ -8,7 +8,7 @@ from migen.build.generic_platform import *
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from misoc.cores import spi as spi_csr
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from misoc.cores import gpio
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from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from misoc.integration.builder import *
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from misoc.targets.sayma_amc import BaseSoC
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from artiq.gateware import rtio
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@ -34,6 +34,7 @@ class Satellite(BaseSoC):
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**kwargs)
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platform = self.platform
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rtio_clk_freq = 150e6
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rtio_channels = []
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for i in range(4):
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@ -54,17 +55,15 @@ class Satellite(BaseSoC):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.transceiver = gth_7series.GTH(
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self.submodules.transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("si5324_clkout"),
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tx_pads=platform.request("sfp_tx"),
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rx_pads=platform.request("sfp_rx"),
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sys_clk_freq=self.clk_freq)
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tx_pads=[platform.request("sfp_tx")],
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rx_pads=[platform.request("sfp_rx")],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer0 = rx0(gth_ultrascale.RXSynchronizer(
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self.transceiver.rtio_clk_freq, initial_phase=180.0))
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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self.transceiver.channels[0], rtio_channels, self.rx_synchronizer0))
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self.csr_devices.append("rx_synchronizer0")
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self.transceiver.channels[0], rtio_channels))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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@ -73,7 +72,7 @@ class Satellite(BaseSoC):
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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self.config["RTIO_FREQUENCY"] = str(self.transceiver.rtio_clk_freq/1e6)
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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si5324_clkin = platform.request("si5324_clkin")
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self.specials += \
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Instance("OBUFDS",
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@ -88,12 +87,13 @@ class Satellite(BaseSoC):
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
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platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
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platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
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rtio_clk_period = 1e9/rtio_clk_freq
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gth = self.transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.transceiver.txoutclk, self.transceiver.rxoutclk)
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gth.txoutclk, gth.rxoutclk)
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def main():
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