forked from M-Labs/artiq
Urukul: flake8 (NFC)
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1a1b454ed9
@ -1,15 +1,15 @@
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from artiq.language.core import kernel, delay, portable
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from artiq.language.units import us, ms
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from numpy import int32, int64
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from numpy import int32
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from artiq.coredevice import spi2 as spi
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SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_END |
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0*spi.SPI_INPUT | 1*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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0*spi.SPI_INPUT | 1*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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# SPI clock write and read dividers
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SPIT_CFG_WR = 2
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@ -52,7 +52,7 @@ CS_DDS_CH3 = 7
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@portable
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def urukul_cfg(rf_sw, led, profile, io_update, mask_nu,
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clk_sel, sync_sel, rst, io_rst):
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clk_sel, sync_sel, rst, io_rst):
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"""Build Urukul CPLD configuration register"""
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return ((rf_sw << CFG_RF_SW) |
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(led << CFG_LED) |
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@ -129,10 +129,10 @@ class CPLD:
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kernel_invariants = {"refclk", "bus", "core", "io_update"}
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def __init__(self, dmgr, spi_device, io_update_device=None,
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dds_reset_device=None, sync_sel=0, clk_sel=0, rf_sw=0,
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refclk=125e6, att=0x00000000, core_device="core"):
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dds_reset_device=None, sync_sel=0, clk_sel=0, rf_sw=0,
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refclk=125e6, att=0x00000000, core_device="core"):
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self.core = dmgr.get(core_device)
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self.core = dmgr.get(core_device)
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self.refclk = refclk
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self.bus = dmgr.get(spi_device)
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@ -144,8 +144,8 @@ class CPLD:
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self.dds_reset = dmgr.get(dds_reset_device)
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self.cfg_reg = urukul_cfg(rf_sw=rf_sw, led=0, profile=0,
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io_update=0, mask_nu=0, clk_sel=clk_sel,
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sync_sel=sync_sel, rst=0, io_rst=0)
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io_update=0, mask_nu=0, clk_sel=clk_sel,
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sync_sel=sync_sel, rst=0, io_rst=0)
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self.att_reg = att
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@kernel
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@ -158,7 +158,7 @@ class CPLD:
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:attr:`cfg_reg`.
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"""
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 24,
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SPIT_CFG_WR, CS_CFG)
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SPIT_CFG_WR, CS_CFG)
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self.bus.write(cfg << 8)
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self.cfg_reg = cfg
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@ -177,7 +177,7 @@ class CPLD:
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:return: The status register value.
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"""
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT, 24,
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SPIT_CFG_RD, CS_CFG)
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SPIT_CFG_RD, CS_CFG)
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self.bus.write(self.cfg_reg << 8)
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return self.bus.read()
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@ -249,7 +249,7 @@ class CPLD:
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:param att_reg: Attenuator setting string (32 bit)
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"""
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 32,
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SPIT_ATT_WR, CS_ATT)
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SPIT_ATT_WR, CS_ATT)
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self.bus.write(att_reg)
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self.att_reg = att_reg
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@ -273,6 +273,6 @@ class CPLD:
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:return: 32 bit attenuator settings
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"""
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT, 32,
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SPIT_ATT_RD, CS_ATT)
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SPIT_ATT_RD, CS_ATT)
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self.bus.write(self.att_reg)
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return self.bus.read()
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