forked from M-Labs/artiq
rtio/sed: centralize all layouts in one file
This commit is contained in:
parent
1b61442bc3
commit
181cb42ba8
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@ -1,19 +1,12 @@
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from migen import *
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from migen import *
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from artiq.gateware.rtio import cri
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from artiq.gateware.rtio import cri
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from artiq.gateware.rtio.sed import layouts
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__all__ = ["LaneDistributor"]
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__all__ = ["LaneDistributor"]
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def layout_lane_io(seqn_width, layout_payload):
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return [
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("we", 1, DIR_M_TO_S),
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("writable", 1, DIR_S_TO_M),
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("seqn", seqn_width, DIR_M_TO_S),
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("payload", [(a, b, DIR_M_TO_S) for a, b in layout_payload])
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]
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# CRI write happens in 3 cycles:
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# CRI write happens in 3 cycles:
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# 1. set timestamp
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# 1. set timestamp
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@ -31,7 +24,7 @@ class LaneDistributor(Module):
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self.cri = cri.Interface()
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self.cri = cri.Interface()
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self.minimum_coarse_timestamp = Signal(64-fine_ts_width)
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self.minimum_coarse_timestamp = Signal(64-fine_ts_width)
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self.lane_io = [Record(layout_lane_io(seqn_width, layout_payload))
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self.lane_io = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
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for _ in range(lane_count)]
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for _ in range(lane_count)]
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# # #
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# # #
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@ -0,0 +1,67 @@
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from migen import *
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from artiq.gateware.rtio import rtlink
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def fifo_payload(channels):
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address_width = max(rtlink.get_address_width(channel.interface)
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for channel in channels)
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data_width = max(rtlink.get_data_width(channel.interface)
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for channel in channels)
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layout = [
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("channel", bits_for(len(channels)-1)),
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("timestamp", 64)
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]
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if address_width:
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layout.append(("address", address_width))
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if data_width:
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layout.append(("data", data_width))
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return layout
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def fifo_ingress(seqn_width, layout_payload):
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return [
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("we", 1, DIR_M_TO_S),
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("writable", 1, DIR_S_TO_M),
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("seqn", seqn_width, DIR_M_TO_S),
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("payload", [(a, b, DIR_M_TO_S) for a, b in layout_payload])
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]
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def fifo_egress(seqn_width, layout_payload):
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return [
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("re", 1, DIR_S_TO_M),
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("readable", 1, DIR_M_TO_S),
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("seqn", seqn_width, DIR_M_TO_S),
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("payload", [(a, b, DIR_M_TO_S) for a, b in layout_payload])
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]
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def output_network_payload(channels):
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fine_ts_width = max(rtlink.get_fine_ts_width(channel.interface)
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for channel in channels)
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address_width = max(rtlink.get_address_width(channel.interface)
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for channel in channels)
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data_width = max(rtlink.get_data_width(channel.interface)
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for channel in channels)
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layout = [("channel", bits_for(len(channels)-1))]
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if fine_ts_width:
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layout.append(("fine_ts", fine_ts_width))
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if address_width:
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layout.append(("address", address_width))
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if data_width:
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layout.append(("data", data_width))
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return layout
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def output_network_node(seqn_width, layout_payload):
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return [
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("valid", 1),
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("seqn", seqn_width),
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("replace_occured", 1),
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("payload", layout_payload)
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]
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@ -3,7 +3,7 @@ from operator import or_
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from migen import *
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from migen import *
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from artiq.gateware.rtio import rtlink
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from artiq.gateware.rtio.sed import layouts
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from artiq.gateware.rtio.sed.output_network import OutputNetwork
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from artiq.gateware.rtio.sed.output_network import OutputNetwork
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@ -17,21 +17,8 @@ class OutputDriver(Module):
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self.busy = Signal()
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self.busy = Signal()
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self.busy_channel = Signal(max=len(channels))
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self.busy_channel = Signal(max=len(channels))
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fine_ts_width = max(rtlink.get_fine_ts_width(channel.interface)
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for channel in channels)
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address_width = max(rtlink.get_address_width(channel.interface)
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for channel in channels)
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data_width = max(rtlink.get_data_width(channel.interface)
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for channel in channels)
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# output network
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# output network
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layout_on_payload = [("channel", bits_for(len(channels)-1))]
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layout_on_payload = layouts.output_network_payload(channels)
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if fine_ts_width:
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layout_on_payload.append(("fine_ts", fine_ts_width))
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if address_width:
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layout_on_payload.append(("address", address_width))
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if data_width:
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layout_on_payload.append(("data", data_width))
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output_network = OutputNetwork(lane_count, seqn_width, layout_on_payload)
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output_network = OutputNetwork(lane_count, seqn_width, layout_on_payload)
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self.submodules += output_network
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self.submodules += output_network
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self.input = output_network.input
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self.input = output_network.input
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@ -1,5 +1,7 @@
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from migen import *
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from migen import *
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from artiq.gateware.rtio.sed import layouts
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__all__ = ["latency", "OutputNetwork"]
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__all__ = ["latency", "OutputNetwork"]
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@ -42,28 +44,19 @@ def latency(lane_count):
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return sum(l for l in range(1, d+1))
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return sum(l for l in range(1, d+1))
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def layout_node_data(seqn_width, layout_payload):
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return [
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("valid", 1),
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("seqn", seqn_width),
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("replace_occured", 1),
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("payload", layout_payload)
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]
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def cmp_wrap(a, b):
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def cmp_wrap(a, b):
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return Mux(a[-2:] == ~b[-2:], a[0], a[:-2] < b[:-2])
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return Mux(a[-2:] == ~b[-2:], a[0], a[:-2] < b[:-2])
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class OutputNetwork(Module):
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class OutputNetwork(Module):
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def __init__(self, lane_count, seqn_width, layout_payload):
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def __init__(self, lane_count, seqn_width, layout_payload):
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self.input = [Record(layout_node_data(seqn_width, layout_payload))
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self.input = [Record(layouts.output_network_node(seqn_width, layout_payload))
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for _ in range(lane_count)]
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for _ in range(lane_count)]
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self.output = None
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self.output = None
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step_input = self.input
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step_input = self.input
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for step in boms_steps_pairs(lane_count):
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for step in boms_steps_pairs(lane_count):
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step_output = [Record(layout_node_data(seqn_width, layout_payload))
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step_output = [Record(layouts.output_network_node(seqn_width, layout_payload))
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for _ in range(lane_count)]
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for _ in range(lane_count)]
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for node1, node2 in step:
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for node1, node2 in step:
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