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gateware: remove one stray CRI arbiter remnant.

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This commit is contained in:
whitequark 2017-04-05 16:38:56 +00:00
parent 464202d0aa
commit 17b5388259
1 changed files with 2 additions and 3 deletions
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5
artiq/gateware/drtio/rt_controller_master.py
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@ -37,7 +37,6 @@ class RTController(Module):
def __init__(self, rt_packet, channel_count, fine_ts_width): def __init__(self, rt_packet, channel_count, fine_ts_width):
self.csrs = _CSRs() self.csrs = _CSRs()
self.cri = cri.Interface() self.cri = cri.Interface()
self.comb += self.cri.arb_gnt.eq(1)
# protocol errors # protocol errors
err_unknown_packet_type = Signal() err_unknown_packet_type = Signal()
@ -45,7 +44,7 @@ class RTController(Module):
signal_fifo_space_timeout = Signal() signal_fifo_space_timeout = Signal()
err_fifo_space_timeout = Signal() err_fifo_space_timeout = Signal()
self.sync.sys_with_rst += [ self.sync.sys_with_rst += [
If(self.csrs.protocol_error.re, If(self.csrs.protocol_error.re,
If(self.csrs.protocol_error.r[0], err_unknown_packet_type.eq(0)), If(self.csrs.protocol_error.r[0], err_unknown_packet_type.eq(0)),
If(self.csrs.protocol_error.r[1], err_packet_truncated.eq(0)), If(self.csrs.protocol_error.r[1], err_packet_truncated.eq(0)),
If(self.csrs.protocol_error.r[2], err_fifo_space_timeout.eq(0)) If(self.csrs.protocol_error.r[2], err_fifo_space_timeout.eq(0))
@ -70,7 +69,7 @@ class RTController(Module):
tsc_correction = Signal(64) tsc_correction = Signal(64)
self.csrs.tsc_correction.storage.attr.add("no_retiming") self.csrs.tsc_correction.storage.attr.add("no_retiming")
self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction) self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction)
self.comb += [ self.comb += [
rt_packet.tsc_value.eq( rt_packet.tsc_value.eq(
self.counter.value_rtio + tsc_correction), self.counter.value_rtio + tsc_correction),
self.csrs.set_time.w.eq(rt_packet.set_time_stb) self.csrs.set_time.w.eq(rt_packet.set_time_stb)