forked from M-Labs/artiq
ttl: Remove error-prone sync() calls
These methods are problematic, as with DMA in the picture, the timestamp member variables did not necessarily reflect the last submitted event timestamp (see GitHub #1113). sync() is only very rarely used in typical experimental code, so the methods are removed without a transition period. Core.wait_until() can be used to busy-wait for a specified RTIO timestamp value on the core device CPU instead.
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@ -35,9 +35,6 @@ class TTLOut:
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self.core = dmgr.get(core_device)
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self.channel = channel
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# in RTIO cycles
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self.o_previous_timestamp = numpy.int64(0)
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@kernel
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def output(self):
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pass
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@ -45,14 +42,6 @@ class TTLOut:
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@kernel
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def set_o(self, o):
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rtio_output(now_mu(), self.channel, 0, 1 if o else 0)
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self.o_previous_timestamp = now_mu()
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@kernel
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def sync(self):
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"""Busy-wait until all programmed level switches have been
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effected."""
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while self.core.get_rtio_counter_mu() < self.o_previous_timestamp:
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pass
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@kernel
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def on(self):
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@ -123,8 +112,6 @@ class TTLInOut:
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self.core = dmgr.get(core_device)
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self.channel = channel
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# in RTIO cycles
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self.o_previous_timestamp = numpy.int64(0)
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self.i_previous_timestamp = numpy.int64(0)
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self.queued_samples = 0
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@ -153,14 +140,6 @@ class TTLInOut:
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@kernel
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def set_o(self, o):
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rtio_output(now_mu(), self.channel, 0, 1 if o else 0)
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self.o_previous_timestamp = now_mu()
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@kernel
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def sync(self):
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"""Busy-wait until all programmed level switches have been
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effected."""
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while self.core.get_rtio_counter_mu() < self.o_previous_timestamp:
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pass
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@kernel
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def on(self):
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