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sma_spi: cri/cd changes

This commit is contained in:
Robert Jördens 2017-04-07 23:57:08 +02:00
parent 1e6e81a19e
commit 16b7f8f50c
1 changed files with 3 additions and 3 deletions
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6
artiq/gateware/targets/kc705_sma_spi.py
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@ -67,8 +67,6 @@ class _RTIOCRG(Module, AutoCSR):
] ]
_sma_spi = [ _sma_spi = [
("sma_spi", 0, ("sma_spi", 0,
Subsignal("clk", Pins("Y23")), # user_sma_gpio_p Subsignal("clk", Pins("Y23")), # user_sma_gpio_p
@ -122,12 +120,14 @@ class SMA_SPI(_NIST_Ions):
self.submodules.rtio_core = rtio.Core(rtio_channels) self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core") self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator() self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if()) self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma") self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared( self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri], [self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri]) [self.rtio_core.cri])
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")