forked from M-Labs/artiq
sma_spi: cri/cd changes
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1e6e81a19e
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16b7f8f50c
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@ -67,8 +67,6 @@ class _RTIOCRG(Module, AutoCSR):
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]
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]
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_sma_spi = [
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_sma_spi = [
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("sma_spi", 0,
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("sma_spi", 0,
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Subsignal("clk", Pins("Y23")), # user_sma_gpio_p
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Subsignal("clk", Pins("Y23")), # user_sma_gpio_p
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@ -122,12 +120,14 @@ class SMA_SPI(_NIST_Ions):
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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[self.rtio_core.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.csr_devices.append("rtio_moninj")
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