forked from M-Labs/artiq
coredevice.spi: cleanup
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@ -1,4 +1,5 @@
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from artiq.language.core import *
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from artiq.language.core import (kernel, portable, seconds_to_mu, now_mu,
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delay_mu)
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from artiq.language.units import MHz
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from artiq.coredevice.rt2wb import rt2wb_write, rt2wb_read_sync
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@ -83,6 +84,11 @@ class SPIMaster:
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SPI_RT2WB_READ, int(2*self.ref_period_mu))
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@kernel
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def get_config_sync(self):
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def _get_config_sync(self):
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return rt2wb_read_sync(now_mu(), self.channel, SPI_CONFIG_ADDR |
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SPI_RT2WB_READ, int(2*self.ref_period_mu))
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@kernel
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def _get_xfer_sync(self):
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return rt2wb_read_sync(now_mu(), self.channel, SPI_XFER_ADDR |
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SPI_RT2WB_READ, int(2*self.ref_period_mu))
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