forked from M-Labs/artiq
spi: cleanup, add frequency_to_div()
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@ -1,4 +1,4 @@
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from artiq.language.core import (kernel, seconds_to_mu, now_mu,
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from artiq.language.core import (kernel, portable, seconds_to_mu, now_mu,
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delay_mu, int)
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from artiq.language.units import MHz
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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@ -57,6 +57,10 @@ class SPIMaster:
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# To chain transfers together, new data must be written before
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# pending transfer's read data becomes available.
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@portable
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def frequency_to_div(self, f):
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return int(1/(f*self.ref_period)) + 1
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@kernel
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def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz):
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"""Set the configuration register.
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@ -105,9 +109,8 @@ class SPIMaster:
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:param write_freq: Desired SPI clock frequency during write bits.
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:param read_freq: Desired SPI clock frequency during read bits.
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"""
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write_div = round(1/(write_freq*self.ref_period))
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read_div = round(1/(read_freq*self.ref_period))
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self.set_config_mu(flags, write_div, read_div)
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self.set_config_mu(flags, self.frequency_to_div(write_freq),
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self.frequency_to_div(read_freq))
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@kernel
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def set_config_mu(self, flags=0, write_div=6, read_div=6):
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@ -174,7 +177,7 @@ class SPIMaster:
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delay_mu(3*self.ref_period_mu)
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@kernel
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def write(self, data):
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def write(self, data=0):
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"""Write data to data register.
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* The ``data`` register and the shift register are 32 bits wide.
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