srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

qc2: swap SPI/TTL, all TTL lines are now In+Out compatible

This commit is contained in:
dhslichter 2016-05-19 10:41:46 +08:00 committed by Sebastien Bourdeauducq
parent 109ddf919e
commit 141edb521a
3 changed files with 21 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
artiq/gateware/nist_qc2.py
View File

@ -9,7 +9,7 @@ __all__ = ["fmc_adapter_io"]
ttl_pins = [
"LA00_CC_P", "LA02_P", "LA00_CC_N", "LA02_N", "LA01_CC_P", "LA01_CC_N", "LA06_P", "LA06_N",
"LA05_P", "LA05_N", "LA10_P", "LA09_P", "LA10_N", "LA09_N", "LA13_P", "LA14_P",
"LA27_P", "LA26_P", "LA27_N", "LA26_N"
"LA13_N", "LA14_N", "LA17_CC_P", "LA17_CC_N"
]
@ -53,19 +53,19 @@ def get_fmc_adapter_io():
("clkout", next(clkout), FPins("FMC:CLK1_M2C_P"),
IOStandard("LVTTL")),
("spi", next(spi),
Subsignal("clk", FPins("FMC:LA13_N")),
Subsignal("mosi", FPins("FMC:LA14_N")),
Subsignal("miso", FPins("FMC:LA17_CC_P")),
Subsignal("cs_n", FPins("FMC:LA17_CC_N")),
IOStandard("LVTTL")),
("spi", next(spi),
Subsignal("clk", FPins("FMC:LA18_CC_P")),
Subsignal("mosi", FPins("FMC:LA18_CC_N")),
Subsignal("miso", FPins("FMC:LA23_P")),
Subsignal("cs_n", FPins("FMC:LA23_N")),
IOStandard("LVTTL")),
("spi", next(spi),
Subsignal("clk", FPins("FMC:LA27_P")),
Subsignal("mosi", FPins("FMC:LA26_P")),
Subsignal("miso", FPins("FMC:LA27_N")),
Subsignal("cs_n", FPins("FMC:LA26_N")),
IOStandard("LVTTL")),
]
return r

28
artiq/gateware/targets/kc705.py
View File

@ -310,27 +310,22 @@ class NIST_QC2(_NIST_Ions):
rtio_channels = []
clock_generators = []
for backplane_offset in 0, 20:
# TTL0-15, 20-35 are In+Out capable
for i in range(16):
phy = ttl_serdes_7series.Inout_8X(
platform.request("ttl", backplane_offset+i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
# TTL16-19, 36-39 are output only
for i in range(16, 20):
phy = ttl_serdes_7series.Output_8X(
platform.request("ttl", backplane_offset+i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# CLK0, CLK1 are for the clock generators, on backplane SMP connectors
for backplane_offset in range(2):
# All TTL channels are In+Out capable
for i in range(40):
phy = ttl_serdes_7series.Inout_8X(
platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
# CLK0, CLK1 are for clock generators, on backplane SMP connectors
for i in range(2):
phy = ttl_simple.ClockGen(
platform.request("clkout", backplane_offset))
platform.request("clkout", i))
self.submodules += phy
clock_generators.append(rtio.Channel.from_phy(phy))
# user SMA on KC705 board
phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
@ -339,6 +334,7 @@ class NIST_QC2(_NIST_Ions):
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# AMS101 DAC on KC705 XADC header - optional
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy

4
doc/manual/core_device.rst
View File

@ -104,9 +104,7 @@ With the QC2 hardware, the TTL lines are mapped as follows:
+--------------------+-----------------------+--------------+
| RTIO channel | TTL line | Capability |
+====================+=======================+==============+
| 0-15, 20-35 | TTL0-15, TTL20-35 | Input+Output |
+--------------------+-----------------------+--------------+
| 16-19, 36-39 | TTL16-19, TTL36-39 | Output |
| 0-39 | TTL0-39 | Input+Output |
+--------------------+-----------------------+--------------+
| 40 | SMA_GPIO_N | Input+Output |
+--------------------+-----------------------+--------------+