From 13830a27af9708f1bd64e1577d7466f27936e536 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Fri, 24 May 2024 10:50:13 +0800
Subject: [PATCH] riscv: add IRQ control

---
 artiq/firmware/libboard_misoc/riscv32/irq.rs | 49 ++++++++++++++++++++
 artiq/firmware/libboard_misoc/riscv32/mod.rs |  1 +
 2 files changed, 50 insertions(+)
 create mode 100644 artiq/firmware/libboard_misoc/riscv32/irq.rs

diff --git a/artiq/firmware/libboard_misoc/riscv32/irq.rs b/artiq/firmware/libboard_misoc/riscv32/irq.rs
new file mode 100644
index 000000000..3c632e952
--- /dev/null
+++ b/artiq/firmware/libboard_misoc/riscv32/irq.rs
@@ -0,0 +1,49 @@
+use riscv::register::{mie, mstatus};
+
+fn vmim_write(val: usize) {
+    unsafe {
+        asm!("csrw {csr}, {rs}", rs = in(reg) val, csr = const 0xBC0);
+    }
+}
+
+fn vmim_read() -> usize {
+    let r: usize;
+    unsafe {
+        asm!("csrr {rd}, {csr}", rd = out(reg) r, csr = const 0xBC0);
+    }
+    r
+}
+
+fn vmip_read() -> usize {
+    let r: usize;
+    unsafe {
+        asm!("csrr {rd}, {csr}", rd = out(reg) r, csr = const 0xFC0);
+    }
+    r
+}
+
+pub fn enable_interrupts() {
+    unsafe {
+        mstatus::set_mie();
+        mie::set_mext();
+    }
+}
+
+pub fn disable_interrupts() {
+    unsafe {
+        mstatus::clear_mie();
+        mie::clear_mext();
+    }
+}
+
+pub fn enable(id: u32) {
+    vmim_write(vmim_read() | (1 << id));
+}
+
+pub fn disable(id: u32) {
+    vmim_write(vmim_read() & !(1 << id));
+}
+
+pub fn is_pending(id: u32) -> bool {
+    (vmip_read() >> id) & 1 == 1
+}
diff --git a/artiq/firmware/libboard_misoc/riscv32/mod.rs b/artiq/firmware/libboard_misoc/riscv32/mod.rs
index a8f498adc..2408c8664 100644
--- a/artiq/firmware/libboard_misoc/riscv32/mod.rs
+++ b/artiq/firmware/libboard_misoc/riscv32/mod.rs
@@ -1,3 +1,4 @@
 pub mod cache;
 pub mod boot;
+pub mod irq;
 pub mod pmp;