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sawg: reduce f0 oscillator width to 32

This commit is contained in:
Robert Jördens 2016-11-19 17:07:07 +01:00
parent 04813ea29b
commit 12e39a64cf
1 changed files with 1 additions and 1 deletions
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2
artiq/gateware/dsp/sawg.py
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@ -147,7 +147,7 @@ class Channel(Module, SatAddMixin):
self.submodules.a1 = a1 = SplineParallelDDS(widths, orders)
self.submodules.a2 = a2 = SplineParallelDDS(widths, orders)
self.submodules.b = b = SplineParallelDUC(
widths._replace(a=len(a1.xo[0])), orders,
widths._replace(a=len(a1.xo[0]), f=widths.f - width), orders,
parallelism=parallelism, a_delay=-a1.latency)
cfg = Config(widths.a)
u = Spline(width=widths.a, order=orders.a)