srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

Merge pull request #1980 from FabianSchwartau/fix_phaser_init_delays 

Fixed two too low delay values in Phaser init
This commit is contained in:
Robert Jördens 2022-10-19 15:55:11 +02:00 committed by GitHub
parent 286f151d9a d5e267fadf
commit 118b7aca1d
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/coredevice/phaser.py
View File

@ -275,7 +275,7 @@ class Phaser:
for data in self.dac_mmap:
self.dac_write(data >> 16, data)
delay(40*us)
delay(120*us)
self.dac_sync()
delay(40*us)
@ -662,7 +662,7 @@ class Phaser:
.. note:: Synchronising the NCO clears the phase-accumulator
"""
config1f = self.dac_read(0x1f)
delay(.1*ms)
delay(.4*ms)
self.dac_write(0x1f, config1f & ~int32(1 << 1))
self.dac_write(0x1f, config1f | (1 << 1))