jesd204_tools: get the Vivado timing analyzer to behave

2019-01-03 20:22:35 +08:00 · 2019-01-03 20:22:35 +08:00 · 10ebf63c47
parent d6a3172a3e
commit 10ebf63c47
1 changed files with 1 additions and 0 deletions
--- a/artiq/gateware/jesd204_tools.py
+++ b/artiq/gateware/jesd204_tools.py
@ -37,6 +37,7 @@ class UltrascaleCRG(Module, AutoCSR):
        ]

        if use_rtio_clock:
+            self.cd_jesd.clk.attr.add("keep")
            self.comb += self.cd_jesd.clk.eq(ClockSignal("rtio"))
        else:
            self.specials += Instance("BUFG_GT", i_I=refclk2, o_O=self.cd_jesd.clk)