forked from M-Labs/artiq
pipistrello: move the spi channel like kc705
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40c1cde2e2
commit
104d641c59
@ -192,17 +192,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
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self.config["DDS_CHANNEL_COUNT"] = 8
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self.config["DDS_AD9858"] = True
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dds_pins = platform.request("dds")
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self.comb += dds_pins.p.eq(0)
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phy = dds.AD9858(dds_pins, 8)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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spi_pins = Module()
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spi_pins.cs_n = pmod.d[0]
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spi_pins.mosi = pmod.d[1]
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@ -214,6 +203,17 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=32, ififo_depth=32))
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self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
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self.config["DDS_CHANNEL_COUNT"] = 8
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self.config["DDS_AD9858"] = True
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dds_pins = platform.request("dds")
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self.comb += dds_pins.p.eq(0)
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phy = dds.AD9858(dds_pins, 8)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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@ -153,5 +153,5 @@ Interface Type 2 (SPI) and 2A (expanded SPI):
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+--------------+--------+--------+--------+--------+
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| RTIO channel | CS_N | MOSI | MISO | CLK |
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+==============+========+========+========+========+
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| 28 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 |
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| 27 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 |
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+--------------+--------+--------+--------+--------+
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