From 101ed5d534bfe697d5fbfaede98020e555775788 Mon Sep 17 00:00:00 2001 From: David Nadlinger Date: Wed, 9 Jan 2019 03:40:15 +0000 Subject: [PATCH] examples: Fix DRTIO destination indices (#1231) Using the default routing table, links numbers and destinations are offset by 1, as destination 0 is local RTIO. --- .../kasli_sawgmaster/repository/sines_2sayma.py | 12 +++++++++--- .../repository/sines_urukul_sayma.py | 11 +++++++++-- .../sayma_masterdac/repository/sines_drtio.py | 5 +++-- 3 files changed, 21 insertions(+), 7 deletions(-) diff --git a/artiq/examples/kasli_sawgmaster/repository/sines_2sayma.py b/artiq/examples/kasli_sawgmaster/repository/sines_2sayma.py index b6bc7884c..fab0c3693 100644 --- a/artiq/examples/kasli_sawgmaster/repository/sines_2sayma.py +++ b/artiq/examples/kasli_sawgmaster/repository/sines_2sayma.py @@ -6,12 +6,18 @@ class Sines2Sayma(EnvExperiment): self.setattr_device("core") self.sawgs = [self.get_device("sawg"+str(i)) for i in range(16)] + @kernel + def drtio_is_up(self): + for i in range(3): + if not self.core.get_rtio_destination_status(i): + return False + return True + @kernel def run(self): while True: print("waiting for DRTIO ready...") - while not (self.core.get_rtio_destination_status(0) and - self.core.get_rtio_destination_status(1)): + while not self.drtio_is_up(): pass print("OK") @@ -27,5 +33,5 @@ class Sines2Sayma(EnvExperiment): # Do not use a sub-multiple of oscilloscope sample rates. sawg.frequency0.set(9*MHz) - while self.core.get_rtio_destination_status(0) and self.core.get_rtio_destination_status(1): + while self.drtio_is_up(): pass diff --git a/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py b/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py index 9b9ab68de..c23ea99a6 100644 --- a/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py +++ b/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py @@ -8,6 +8,13 @@ class SinesUrukulSayma(EnvExperiment): self.urukul_chs = [self.get_device("urukul0_ch" + str(i)) for i in range(4)] self.sawgs = [self.get_device("sawg"+str(i)) for i in range(8)] + @kernel + def drtio_is_up(self): + for i in range(2): + if not self.core.get_rtio_destination_status(i): + return False + return True + @kernel def run(self): # Note: when testing sync, do not reboot Urukul, as it is not @@ -23,7 +30,7 @@ class SinesUrukulSayma(EnvExperiment): while True: print("waiting for DRTIO ready...") - while not self.core.get_rtio_destination_status(0): + while not self.drtio_is_up(): pass print("OK") @@ -38,5 +45,5 @@ class SinesUrukulSayma(EnvExperiment): sawg.amplitude1.set(.4) sawg.frequency0.set(9*MHz) - while self.core.get_rtio_destination_status(0): + while self.drtio_is_up(): pass diff --git a/artiq/examples/sayma_masterdac/repository/sines_drtio.py b/artiq/examples/sayma_masterdac/repository/sines_drtio.py index 70a7b3484..ea1060940 100644 --- a/artiq/examples/sayma_masterdac/repository/sines_drtio.py +++ b/artiq/examples/sayma_masterdac/repository/sines_drtio.py @@ -10,8 +10,9 @@ class SAWGTestDRTIO(EnvExperiment): @kernel def run(self): core_log("waiting for DRTIO ready...") - while not self.core.get_rtio_destination_status(0): - pass + for i in range(3): + while not self.core.get_rtio_destination_status(i): + pass core_log("OK") self.core.reset()