From 0ffc752310451efe48db44517e09d2e482eb691b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 20 Jul 2017 22:18:21 +0800 Subject: [PATCH] spi: fix typo in doc --- artiq/coredevice/spi.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/coredevice/spi.py b/artiq/coredevice/spi.py index e2c551ff5..e5e48d690 100644 --- a/artiq/coredevice/spi.py +++ b/artiq/coredevice/spi.py @@ -74,7 +74,7 @@ class SPIMaster: def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz): """Set the configuration register. - * If ``config.cs_polarity`` == 0 (```cs`` active low, the default), + * If ``config.cs_polarity`` == 0 (``cs`` active low, the default), "``cs_n`` all deasserted" means "all ``cs_n`` bits high". * ``cs_n`` is not mandatory in the pads supplied to the gateware core. Framing and chip selection can also be handled independently